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| KM641001A |
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 SAMSUNG
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6 page 
KM641001A CMOS SRAM PRELIMINARY Rev 5.0 - 6 - February 1998 NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock) Address CS tWP(2) tDW tDH Valid Data WE Data in Data out tWC tWR(5) tAW tCW(3) High-Z(8) High-Z OE tOHZ(6) tAS(4) TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed) Address CS tWP1(2) tDW tDH tOW tWHZ(6) Valid Data WE Data in Data out tWC tAS(4) tWR(5) tAW tCW(3) (10) (9) High-Z(8) High-Z |
