11

1996 ISP Encyclopedia

Specifications ispLSI and pLSI 1016E

ispLSI 1016E Shift Register Layout

E2CMOS Cell Array

High Order Shift Register

Low Order Shift Register

79...

159...

...0

...80

D

A

T

A

D

A

T

A

Data In

(SDI)

SDO

109

.

.

.

.

.

.

0

SDO

SDI

0182B-16

Note: A logic “1” in the Address Shift Register bit position enables the row for programming or verification.

A logic “0” disables it.