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MSP430F2234IDAR Datasheet(PDF) 10 Page - Texas Instruments |
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MSP430F2234IDAR Datasheet(HTML) 10 Page - Texas Instruments |
10 / 85 page MSP430x22x2, MSP430x22x4 MIXED SIGNAL MICROCONTROLLER SLAS504B − JULY 2006 − REVISED JULY 2007 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions, MSP430x22x4 (Continued) TERMINAL NAME DA RHA I/O DESCRIPTION NAME NO. NO. I/O DESCRIPTION P3.5/ UCA0RXD/UCA0SOMI 26 24 I/O General-purpose digital I/O pin USCI_A0 receive data input in UART mode, slave out/master in in SPI mode P3.6/A6/OA0I2 27 25 I/O General-purpose digital I/O pin ADC10 analog input A6 / OA0 analog input I2 P3.7/A7/OA1I2 28 26 I/O General-purpose digital I/O pin ADC10 analog input A7 / OA1 analog input I2 P4.0/TB0 17 15 I/O General-purpose digital I/O pin Timer_B, capture: CCI0A input, compare: OUT0 output P4.1/TB1 18 16 I/O General-purpose digital I/O pin Timer_B, capture: CCI1A input, compare: OUT1 output P4.2/TB2 19 17 I/O General-purpose digital I/O pin Timer_B, capture: CCI2A input, compare: OUT2 output P4.3/TB0/ A12/OA0O 20 18 I/O General-purpose digital I/O pin Timer_B, capture: CCI0B input, compare: OUT0 output ADC10 analog input A12 / OA0 analog output P4.4/TB1 A13/OA1O 21 19 I/O General-purpose digital I/O pin Timer_B, capture: CCI1B input, compare: OUT1 output ADC10 analog input A13 / OA1 analog output P4.5/TB2 A14/OA0I3 22 20 I/O General-purpose digital I/O pin Timer_B, compare: OUT2 output ADC10 analog input A14 / OA0 analog input I3 P4.6/TBOUTH A15/OA1I3 23 21 I/O General-purpose digital I/O pin Timer_B, switch all TB0 to TB3 outputs to high impedance ADC10 analog input A15 / OA1 analog input I3 P4.7/TBCLK 24 22 I/O General-purpose digital I/O pin Timer_B, clock signal TBCLK input RST/NMI/SBWTDIO 7 5 I Reset or nonmaskable interrupt input Spy-Bi-Wire test data input/output during programming and test TEST/SBWTCK 1 37 I Selects test mode for JTAG pins on Port1. The device protection fuse is connected to TEST. Spy-Bi-Wire test clock input during programming and test DVCC 2 38, 39 Digital supply voltage AVCC 16 14 Analog supply voltage DVSS 4 1, 4 Digital ground reference AVSS 15 13 Analog ground reference QFN Pad NA Package Pad NA QFN package pad connection to DVSS recommended. † TDO or TDI is selected via JTAG instruction. NOTE: If XOUT/P2.7/CA7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset. |
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