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TDA3755 Datasheet(PDF) 8 Page - NXP Semiconductors

Part # TDA3755
Description  PAL/NTSC/SECAM synchronization processor for video recorders
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

TDA3755 Datasheet(HTML) 8 Page - NXP Semiconductors

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June 1986
8
Philips Semiconductors
Product specification
PAL/NTSC/SECAM synchronization
processor for video recorders
TDA3755
Notes to the characteristics
1. Or not connected.
2. The sync separator input signal is shown in Fig.2.
3. The black level and the top sync level are detected internally and stored in capacitors at pin 2 and pin 3 respectively.
4. The vertical sync pulse output is disabled by mute.
5. In test picture mode the synthetic sync pulse is fed to output pin 1 and the vertical pulse consists of an uninterrupted
block pulse of 192
µs triggering at every transition of head pulse (HP) at pin 9. The timing of test picture and synthetic
sync pulse is shown in Fig.3.
6. Oscillator adjustment during test picture mode made only, at V11-15 > 4,8 V, V7-15 = 0 V and V4-15 > 2 V or open
circuit; measurement is fosc / 8 at output pin 8.
7. The holding range and catching range are both determined by the resistor connected between pin 5 and pin 6.
8. The phase of the lower subcarrier is switched in accordance with the VHS standard. PNP emitter follower, internal
resistive load of 10 k
Ω (typ.) to VP.
9. The output voltage at pin 5 is disabled during test picture mode.
10. The burst gating pulse is superimposed on an uninterrupted horizontal pulse. It is suppressed 16 times starting with
every transition of the head pulse at pin 9. If a vertical pulse is detected during that time the burst gating pulses are
additionally suppressed until line 12 and line 324 respectively. In any event the number of suppressed burst gating
pulses is even.
11. The timing of the upper part of the sandcastle pulse is determined by the components connected to pin 12 (Fig.4)
and is independent of supply voltage variations.
12. The fast phase correction pulses have to be in the burst gating reference pulse. For any HIGH to LOW transitions of
the correction pulse the phase is corrected by
−90° if the head pulse input is LOW and by +90° if the head pulse input
is HIGH.
13. Subcarrier phase switching is detailed in Table 1.
Subcarrier is 40,000
× fH for NTSC state and 40,125 × fH for PAL state.
Table 1
Subcarrier phase switching
STILL
PAL
NTSC
PICTURE INPUT
HP = HIGH
HP = LOW
HP = HIGH
HP = LOW
HIGH
−90°−90°−90°−90°
not connected
0
°−90°+90°−90°
LOW
0
°
0
°+90°+90°


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