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SN74LV4040ADE4 Datasheet(PDF) 2 Page - Texas Instruments |
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SN74LV4040ADE4 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 17 page SN54LV4040A, SN74LV4040A 12BIT ASYNCHRONOUS BINARY COUNTERS SCES226I − APRIL 1999 − REVISED MAY 2005 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) The ’LV4040A devices are 12-bit asynchronous binary counters with the outputs of all stages available externally. A high level at the clear (CLR) input asynchronously clears the counter and resets all outputs low. The count is advanced on a high-to-low transition at the clock (CLK) input. Applications include time-delay circuits, counter controls, and frequency-dividing circuits. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. FUNCTION TABLE (each buffer) INPUTS FUNCTION CLK CLR FUNCTION ↑ L No change ↓ L Advance to next stage X H All outputs L logic diagram (positive logic) Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages. R T R T R T R T R T R T R T R T R T R T R T R T 95 3 2 4 13 12 14 15 1 11 10 CLR CLK QA QD QE QH QK QL QF QG QI QJ 7 QB 6 QC |
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