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M30620FCPFP Datasheet(PDF) 51 Page - Renesas Technology Corp |
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M30620FCPFP Datasheet(HTML) 51 Page - Renesas Technology Corp |
51 / 87 page M16C/62 Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics (M16C/62P) VCC1 = VCC2 = 5V 4 8 f o 3 0 0 2 , 7 0 . v o N 0 1 . 2 . v e R page 51 Figure 5.9 Timing Diagram (8) Memory Expansion Mode, Microprocessor Mode (For 1- or 2-wait setting, external area access and multiplex bus selection) BCLK CSi td(BCLK-CS) 25ns.max ADi td(BCLK-AD) 25ns.max ALE th(BCLK-ALE) -4ns.min RD 25ns.max th(BCLK-RD) 0ns.min th(BCLK-AD) 4ns.min th(BCLK-CS) 4ns.min tcyc th(RD-CS) th(RD-AD) BHE ADi /DBi th(RD-DB) 0ns.min td(AD-ALE) Read timing td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min BCLK CSi td(BCLK-CS) 25ns.max ADi td(BCLK-AD) 25ns.max ALE 25ns.max th(BCLK-ALE) -4ns.min th(BCLK-AD) 4ns.min th(BCLK-CS) 4ns.min tcyc th(WR-AD) BHE td(BCLK-DB) 40ns.max 4ns.min th(BCLK-DB) td(DB-WR) th(WR-DB) ADi /DBi Data output WR,WRL, WRH Write timing Address (0.5 X tcyc-10)ns.min Address Data input 40ns.min (0.5 X tcyc-10)ns.min td(BCLK-ALE) td(BCLK-RD) (0.5 X tcyc-10)ns.min th(WR-CS) Address td(AD-ALE) (0.5 X tcyc-25)ns.min (1.5 X tcyc-40)ns.min (0.5 X tcyc-10)ns.min td(BCLK-ALE) (0.5 X tcyc-25)ns.min Address 25ns.max tsu(DB-RD) tac3(RD-DB) (0.5 X tcyc-10)ns.min (0.5 X tcyc-15)ns.min td(AD-RD) 0ns.min tdZ(RD-AD) 8ns.max td(AD-WR) 0ns.min Measuring conditions • VCC1=VCC2=5V • Input timing voltage : VIL=0.8V, VIH=2.0V • Output timing voltage : VOL=0.4V, VOH=2.4V th(ALE-AD) (1.5 X tcyc-45)ns.max tcyc= 1 f(BCLK) |
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