K4M283233H - F(H)N/G/L/F

7

Mobile SDRAM

January 2006

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

NOTES:

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. Minimum tRDL=2CLK and tDAL(= tRDL + tRP) is required to complete both of last data write command(tRDL) and precharge command(tRP).

4. All parts allow every cycle column address change.

5. In case of row precharge interrupt, auto precharge and read burst stop.

6. Maximum burst refresh cycle : 8

Parameter

Symbol

Version

Unit

Note

-60

-75

-7L

Row active to row active delay

12

15

15

ns

1

RAS to CAS delay

18

18

22.5

ns

1

Row precharge time

18

18

22.5

ns

1

Row active time

42

45

45

ns

1

100

us

Row cycle time

60

63

67.5

ns

1

Last data in to row precharge

2

CLK

2

Last data in to Active delay

tRDL + tRP

-

3

Last data in to new col. address delay

1

CLK

2

Last data in to burst stop

1

CLK

2

Col. address to col. address delay

1

CLK

4

Number of valid output data

CAS latency=3

2

ea

5

Number of valid output data

CAS latency=2

1

Number of valid output data

CAS latency=1

0