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FWIXC1100BD Datasheet(PDF) 10 Page - Intel Corporation |
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FWIXC1100BD Datasheet(HTML) 10 Page - Intel Corporation |
10 / 134 page Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor March 2005 Datasheet 10 Document Number: 252479, Revision: 005 DDR Double Data Rate DES Data-Encryption Standard DMA Direct Memory Access DSP Digital Signal Processor E1 Euro 1 trunk line FIFO First In First Out GCI General Circuit Interface GPIO General-purpose input/output HDLC High-level Data Link Control HPI (Texas Instruments*) Host Port Interfaces HSS High-Speed Serial (port) LSb Least-Significant bit LSB Least-Significant Byte MAC Media Access Controller MDIO Management Data Input/Output MII Media-Independent Interface MMU Memory Management Unit MSb Most-Significant bit MSB Most-Significant Byte NPE Network Processor Engine PCI Peripheral Component Interconnect PHY Physical Layer (Layer 1) Interface Reserved A field that may be used by an implementation. Software should not modify reserved fields or depend on any values in reserved fields. RX Receive (HSS is receiving from off-chip) SRAM Static Random Access Memory SDRAM Synchronous Dynamic Random Access Memory T1 Type 1 trunk line TX Transmit (HSS is transmitting off-chip) UART Universal Asynchronous Receiver-Transmitter USB Universal Serial Bus UTOPIA Universal Test and Operations PHY Interface for ATM WAN Wide Area Network Table 2. Terminology and Acronyms (Continued) Acronym/ Terminology Description |
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