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FWIXP422BB Datasheet(PDF) 47 Page - Intel Corporation |
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FWIXP422BB Datasheet(HTML) 47 Page - Intel Corporation |
47 / 134 page Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet March 2005 Document Number: 252479, Revision: 005 47 GPIO[13] Z Z I/O General purpose input/output pins. May be configured as an input or an output. Default after reset is to be configured as inputs. Should be pulled low using a 10-K Ω resistor when not being utilized in the system. GPIO[14] Z Z I/O Can be configured similar to GPIO Pin 13 or as a clock output. Configuration as an output clock can be set at various speeds of up to 33.33 MHz with various duty cycles. Configured as an input, upon reset. Should be pulled low though a 10-K Ω resistor when not being utilized in the system. GPIO[15] Z CLKOU T/VO I/O Can be configured similar to GPIO Pin 13 or as a clock output. Configuration as an output clock can be set at various speeds of up to 33.33 MHz with various duty cycles. Configured as an output, upon reset. Can be used to clock the expansion interface, after reset. Should be pulled low though a 10-K Ω resistor when not being utilized in the system. Table 17. JTAG Interface Name Power On Reset1 Reset2 Type† Description JTG_TMS H VI/PE I Test mode select for the IEEE 1149.1 JTAG interface. JTG_TDI H VI/PE I Input data for the IEEE 1149.1 JTAG interface. JTG_TDO Z VO O Output data for the IEEE 1149.1 JTAG interface. JTG_TRST_N H VI/PE I Used to reset the IEEE 1149.1 JTAG interface. The JTG_TRST_N signal must be asserted (driven low) during power-up, otherwise the TAP controller may not be initialized properly, and the processor may be locked. When the JTAG interface is not being used, the signal must be pulled low using a 10-K Ω resistor. JTG_TCK Z VI I Used as the clock for the IEEE 1149.1 JTAG interface. 1. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. 2. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. † For a legend of the Type codes, see Table 5 on page 33. Table 16. GPIO Interface (Sheet 2 of 2) Name Power On Reset1 Reset2 Type† Description 1. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. 2. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. † For a legend of the Type codes, see Table 5 on page 33. |
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