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FWIXP422BB Datasheet(PDF) 46 Page - Intel Corporation

Part # FWIXP422BB
Description  Intel짰 IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

FWIXP422BB Datasheet(HTML) 46 Page - Intel Corporation

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Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
March 2005
Datasheet
46
Document Number: 252479, Revision: 005
Table 14.
USB Interface
Name
Power
On
Reset1
Reset2
Type
Description
USB_DPOS
Z
Z
I/O
Positive signal of the differential USB receiver/driver.
USB_DNEG
Z
Z
I/O
Negative signal of the differential USB receiver/driver.
1.
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.
2.
After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of
PLL_LOCK, all signals reflect the value shown in the RESET column.
For a legend of the Type codes, see Table 5 on page 33.
Table 15.
Oscillator Interface
Name
Power
On
Reset1
Reset2
Type
Description
OSC_IN
I
33.33 MHz, sinusoidal crystal input signal. Can be driven by an
oscillator.
OSC_OUT
O
33.33 MHz, sinusoidal crystal output signal. Left disconnected
when being driven by an oscillator.
1.
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.
2.
After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of
PLL_LOCK, all signals reflect the value shown in the RESET column.
For a legend of the Type codes, see Table 5 on page 33.
Table 16.
GPIO Interface (Sheet 1 of 2)
Name
Power
On
Reset1
Reset2
Type
Description
GPIO[12:0]
Z
Z
I/O
General purpose Input/Output pins. May be configured as an input
or an output. As an input, each signal may be configured a
processor interrupt. Default after reset is to be configured as inputs.
Should be pulled low using a 10-K
Ω resistor when not being utilized
in the system.
1.
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.
2.
After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of
PLL_LOCK, all signals reflect the value shown in the RESET column.
For a legend of the Type codes, see Table 5 on page 33.


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