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FWIXP422BB Datasheet(PDF) 40 Page - Intel Corporation

Part # FWIXP422BB
Description  Intel짰 IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

FWIXP422BB Datasheet(HTML) 40 Page - Intel Corporation

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Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
March 2005
Datasheet
40
Document Number: 252479, Revision: 005
Table 10.
MII Interfaces (Sheet 1 of 2)
Name
Power
On
Reset1
Reset2
Type
Description
ETH_TXCLK0
Z
VI
I
Externally supplied transmit clock.
25 MHz for 100 Mbps operation
2.5 MHz for 10 Mbps
Should be pulled low through a 10-K
Ω resistor when not
being utilized in the system.
ETH_TXDATA0[3:0]
Z
0
O
Transmit data bus to PHY, asserted synchronously with
respect to ETH_TXCLK0.
ETH_TXEN0
Z
0
O
Indicates that the PHY is being presented with nibbles on
the MII interface. Asserted synchronously, with respect to
ETH_TXCLK0, at the first nibble of the preamble and
remains asserted until all the nibbles of a frame are
presented.
ETH_RXCLK0
Z
VI
I
Externally supplied receive clock.
25 MHz for 100 Mbps operation
2.5 MHz for 10 Mbps
Should be pulled low through a 10-K
Ω resistor when not
being utilized in the system.
ETH_RXDATA0[3:0]
Z
VI
I
Receive data bus from PHY, data sampled synchronously
with respect to ETH_RXCLK0
Should be pulled low through a 10-K
Ω resistor when
not being utilized in the system.
ETH_RXDV0
Z
VI
I
Receive data valid, used to inform the MII interface that the
Ethernet PHY is sending data. Should be pulled low
through a 10-K
Ω resistor when not being utilized in the
system.
ETH_COL0
Z
VI
I
Asserted by the PHY when a collision is detected by the
PHY. Should be pulled low through a 10-K
Ω resistor when
not being utilized in the system.
ETH_CRS0
Z
VI
I
Asserted by the PHY when the transmit medium or receive
medium is active. De-asserted when both the transmit and
receive medium are idle. Remains asserted throughout the
duration of a collision condition. PHY asserts CRS
asynchronously and de-asserts synchronously, with
respect to ETH_RXCLK0. Should be pulled low through a
10-K
Ω resistor when not being utilized in the system.
ETH_MDIO
Z
Z
I/O
Management data output. Provides the write data to both
PHY devices connected to each MII interface.
An external 1.5-K
Ω pull-up resistor is required.
Note:
If interfacing with a single Intel® LXT972 Fast Ethernet
Transceiver, and a 1.5K pull-up resistor is not used, the
NPE will ‘see’ 32 PHYs on the MII interface.
Should be pulled low through a 10-K
Ω resistor when not
being utilized in the system.
1.
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.
2.
After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of
PLL_LOCK, all signals reflect the value shown in the RESET column.
For a legend of the Type codes, see Table 5 on page 33.


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