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FWIXP422BB Datasheet(PDF) 36 Page - Intel Corporation

Part # FWIXP422BB
Description  Intel짰 IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

FWIXP422BB Datasheet(HTML) 36 Page - Intel Corporation

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Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
March 2005
Datasheet
36
Document Number: 252479, Revision: 005
Table 7.
PCI Controller (Sheet 1 of 2)
Name
Power
on
Reset1
Reset2 Type
Description
PCI_AD[31:0]
Z
Z
I/O
PCI Address/Data bus used to transfer address and bidirectional
data to and from multiple PCI devices.
Should be pulled low with a 10-K
Ω resistor when not being
utilized in the system.
PCI_CBE_N[3:0]
Z
Z
I/O
PCI Command/Byte Enables is used as a command word during
PCI address cycles and as byte enables for data cycles.
Should be pulled high with a 10-K
Ω resistor when not being
utilized in the system.
PCI_PAR
Z
Z
I/O
PCI Parity used to check parity across the 32 bits of PCI_AD and
the four bits of PCI_CBE_N.
Should be pulled low with a 10-K
Ω resistor when not being
utilized in the system.
PCI_FRAME_N
Z
Z
I/O
PCI Cycle Frame used to signify the beginning and duration of a
transaction. The signal will be inactive prior to or during the final
data phase of a given transaction.
Should be pulled high with a 10-K
Ω resistor when not being
utilized in the system.
PCI_TRDY_N
Z
Z
I/O
PCI Target Ready informs that the target of the PCI bus is ready
to complete the current data phase of a given transaction.
Should be pulled high with a 10-K
Ω resistor when not being
utilized in the system.
PCI_IRDY_N
Z
Z
I/O
PCI Initiator Ready informs the PCI bus that the initiator is ready
to complete the transaction.
Should be pulled high with a 10-K
Ω resistor when not being
utilized in the system.
PCI_STOP_N
Z
Z
I/O
PCI Stop indicates that the current target is requesting the
current initiator to stop the current transaction.
Should be pulled high with a 10-K
Ω resistor when not being
utilized in the system.
PCI_PERR_N
Z
Z
I/O
PCI Parity Error asserted when a PCI parity error is detected —
between the PCI_PAR and associated information on the
PCI_AD bus and PCI_CBE_N — during all PCI transactions,
except for Special Cycles. The agent receiving data will drive this
signal.
Should be pulled high with a 10-K
Ω resistor when not being
utilized in the system.
PCI_SERR_N
Z
Z
I/OD
PCI System Error asserted when a parity error occurs on special
cycles or any other error that will cause the PCI bus not to
function properly. This signal can function as an input or an open
drain output.
Should be pulled high with a 10-K
Ω resistor when not being
utilized in the system.
1.
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.
2.
After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of
PLL_LOCK, all signals reflect the value shown in the RESET column.
For a legend of the Type codes, see Table 5 on page 33.


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