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M30622M6P Datasheet(PDF) 52 Page - Renesas Technology Corp |
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M30622M6P Datasheet(HTML) 52 Page - Renesas Technology Corp |
52 / 87 page VCC1 = VCC2 = 5V M16C/62 Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics (M16C/62P) 4 8 f o 3 0 0 2 , 7 0 . v o N 0 1 . 2 . v e R page 52 Figure 5.10 Timing Diagram (9) Read timing Write timing Memory Expansion Mode, Microprocessor Mode (For 3-wait setting, external area access and multiplex bus selection) BCLK CSi ALE RD ADi /DBi ADi BHE BCLK CSi ALE ADi /DBi tcyc td(BCLK-AD) 25ns.max tcyc Data output th(BCLK-CS) 4ns.min td(BCLK-CS) 25ns.max td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min tsu(DB-RD) 40ns.min th(RD-DB) 0ns.min th(RD-AD) (0.5 X tcyc-10)ns.min th(BCLK-AD) 4ns.min td(BCLK-CS) 25ns.max td(BCLK-AD) 25ns.max th(BCLK-DB) 4ns.min th(BCLK-WR) 0ns.min th(WR-AD) (0.5 X tcyc-10)ns.min th(BCLK-AD) 4ns.min th(BCLK-CS) 4ns.min td(BCLK-ALE) 25ns.max td(BCLK-WR) 25ns.max th(WR-DB) (0.5 X tcyc-10)ns.min Data input Address Address ADi BHE WR, WRL WRH Measuring conditions • VCC1=VCC2=5V • Input timing voltage : VIL=0.8V, VIH=2.0V • Output timing voltage : VOL=0.4V, VOH=2.4V td(AD-ALE) (0.5 X tcyc-25)ns.min td(AD-RD) 0ns.min tdZ(RD-AD) 8ns.max tac3(RD-DB) td(BCLK-DB) 40ns.max (0.5 X tcyc-10)ns.min th(WR-CS) td(DB-WR) (2.5 X tcyc-40)ns.min td(AD-WR) 0ns.min th(RD-CS) (0.5 X tcyc-10)ns.min td(AD-ALE) (0.5 X tcyc-25)ns.min (2.5 X tcyc-45)ns.max tcyc= 1 f(BCLK) (no multiplex) (no multiplex) th(ALE-AD) (0.5 X tcyc-15)ns.min th(BCLK-ALE) -4ns.min |
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