 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
IDT72V3662L10PQF Datasheet(PDF) 3 Page - Integrated Device Technology |
|
||||||||||||||||||||||||||||||
IDT72V3662L10PQF Datasheet(HTML) 3 Page - Integrated Device Technology |
|
|
3 / 29 page  3 COMMERCIALTEMPERATURERANGE IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 PIN CONFIGURATION (CONTINUED) TQFP (PN120-1, order code: PF) TOP VIEW 4660 drw03 A35 A34 A33 A32 VCC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 FWFT A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VCC A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 VCC B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VCC B15 B14 B13 B12 GND 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 memory is full or not. The IR and OR functions are selected in the First Word FallThroughmode.IRindicateswhetherornottheFIFOhasavailablememory locations. OR shows whether the FIFO has data available for reading or not. It marks the presence of valid data on the outputs. Each FIFO has a programmable Almost-Empty flag ( AEAandAEB)and a programmable Almost-Full flag ( AFA and AFB). AEA and AEB indicate when a selected number of words remain in the FIFO memory. AFAand AFB indicate when the FIFO contains more than a selected number of words. FFA/IRA, FFB/IRB, AFA and AFB are two-stage synchronized to the port clock that writes data into its array. EFA/ORA, EFB/ORB, AEA and AEB are two-stage synchronized to the port clock that reads data from its array. Programmable offsets for AEA, AEB, AFA and AFB are loaded by using Port A. Three default offset settings are also provided. The AEA and AEB threshold can be set at 8, 16 or 64 locations from the empty boundary and the AFAandAFBthresholdcanbesetat8,16or64locationsfromthefullboundary. All these choices are made using the FS0 and FS1 inputs during Reset. Two or more devices may be used in parallel to create wider data paths. If, at any time, the FIFO is not actively performing a function, the chip will automatically power down. During the power down state, supply current consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol inputs) will immediately take the device out of the power down state. TheIDT72V3652/72V3662/72V3672arecharacterizedforoperationfrom 0 °C to 70°C. Industrial temperature range (-40°C to +85°C) is available by special order. They are fabricated using IDT’s high speed, submicron CMOS technology. |
Similar Part No. - IDT72V3662L10PQF |
|
Similar Description - IDT72V3662L10PQF |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
