Recommended Operating Conditions

56F8025 Digital Signal Controller Product Brief, Rev. 0

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

5

— Output falling and rising edge detection able to generate interrupts

•

Computer Operating Properly (COP)/Watchdog timer capable of selecting different clock sources

•

Up to 35 General-Purpose I/O (GPIO) pins with 5V tolerance

•

Integrated Power-On Reset (POR) and Low-Voltage Interrupt (LVI) module

•

Phase Lock Loop (PLL) provides a high-speed clock to the core and peripherals

•

Clock sources:

— On-chip relaxation oscillator

— External clock: Crystal oscillator, ceramic resonator, and external clock source

•

JTAG/EOnCE debug programming interface for real-time debugging

5

Recommended Operating Conditions

Table 1. Recommended Operating Conditions

Characteristic

Symbol

Notes

Min

Typ

Max

Unit

Supply voltage

33.3

3.6

V

ADC Reference Voltage High

3.0

V

ΔV

DD

-0.1

0

0.1

V

ΔV

SS

-0.3

0

0.3

V

Device Clock Frequency

Using relaxation oscillator

Using external clock source

FSYSCLK

1

0

32

32

MHz

Input Voltage High (digital inputs)

Pin Groups 1, 2

2.0

5.5

V

Input Voltage Low (digital inputs)

Pin Groups 1, 2

-0.3

0.8

V

Oscillator Input Voltage High

XTAL not driven by an external clock

XTAL driven by an external clock source

Pin Group 4

2.0

V

Oscillator Input Voltage Low

Pin Group 4

-0.3

0.8

V

Analog Input Voltage

Pin Group 3

0.0

V