Product Data Sheets
ISD2500 Series
1–81
1
EEPROM Storage
One of the benefits of ISD’s ChipCorder technol-
ogy is the use of on-chip nonvolatile memory,
providing zero-power message storage. The mes-
sage is retained for up to 100 years typically
without power. In addition, the device can be re-
recorded typically over 100,000 times.
Microcontroller Interface
In addition to its simplicity and ease of use, the
ISD2500 Series includes all the interfaces neces-
sary for microcontroller-driven applications. The
address and control lines can be interfaced to a
microcontroller and manipulated to perform a vari-
ety
of
tasks,
including
message
assembly,
message concatenation, predefined fixed mes-
sage segmentation, and message management.
Programming
The ISD2500 Series is also ideal for playback-only
applications, where single or multiple messages
are referenced through buttons, switches, or a
microcontroller. Once the desired message config-
uration is created, duplicates can easily be
generated via an ISD programmer.
PIN DESCRIPTIONS
Voltage Inputs (VCCA, VCCD)
To minimize noise, the analog and digital circuits in
the ISD2500 Series devices use separate power
busses. These voltage busses are brought out to
separate pins and should be tied together as close
to the supply as possible. In addition, these sup-
plies should be decoupled as close to the package
as possible.
Ground Inputs (VSSA, VSSD)
The ISD2500 Series of devices utilizes separate
analog and digital ground busses.
These pins
should be connected separately through a low-
impedance path to power supply ground.
Power Down Input (PD)
When not recording or playing back, the PD pin
should be pulled HIGH to place the part in a very
low power mode (see ISB specification). When
OVF pulses LOW for an overflow condition, PD
should be brought HIGH to reset the address
pointer back to the beginning of the Record/Play-
back
space.
The
PD
pin
has
additional
functionality in the M6 (Push-Button) Operational
ISD2532/40/48/64* DEVICE BLOCK DIAGRAM
* Advance information: ISD2532/40/48/64 devices.
Amp
Pre-
Amp
VCCA
VCCD
A0
A2
A3 A4
A5
A7
A8
A6
OVF P/R
CE EOM
PD
XCLK
ANA IN
ANA OUT
MIC
MIC REF
AGC
256 K Cell
Nonvolatile
Multilevel Storage
Array
Amp
AUX IN
SP+
SP–
VSSA VSSD
A1
Timing
Internal Clock
Power Conditioning
Address Buffers
Device Control
Analog Transceivers
Sampling Clock
Mux
Automatic
Gain Control
(AGC)
5-Pole Active
Antialiasing Filter
5-Pole Active
Smoothing Filter
R
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