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IDT7134LA25CB Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT7134LA25CB Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 11 page IDT7134SA/LA High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges 2 Pin Configurations(1,2,3) NOTES: 1. All VCC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. P48-1 package body is approximately .55 in x .61 in x .19 in. C48-2 package body is approximately .62 in x 2.43 in x .15 in. J52-1 package body is approximately .75 in x .75 in x .17 in. L48-1 package body is approximately .57 in x .57 in x .68 in. F48-1 package body is approxiamtely .75 in x .75 in x .11 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of actual part-marking. A10R 2720 drw 02 I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R I/O7R A9R A8R A7R A6R A4R A3R A2R A1R A0R 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 148 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O 0L I/O 1L I/O 2L I/O 3L I/O 4L I/O 5L I/O 6L I/O 7L IDT7134P or C P48-1(4) & C48-2(4) 48-Pin Top View(5) CEL R/ WL OEL VCC A5R R OE A11R R/ WR CER A11L A10L GND , 2720 drw 03 IDT7134J J52-1(4) 52-Pin PLCC Top View(5) INDEX OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R N/C I/O7R 46 45 44 43 42 41 40 39 38 37 36 35 34 I/O3L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L 8 9 10 11 12 13 14 15 16 17 18 19 20 47 48 49 50 51 52 1 2 3 4 5 6 7 33 32 31 30 29 28 27 26 25 24 23 22 21 2720 drw 04 IDT7134L48 or F L48-1(4) & F48-1(4) 48-Pin LCC/Flatpack Top View(5) INDEX 65 4 3 2 1 48 47 46 45 44 43 19 20 21 22 23 25 26 27 28 29 30 24 A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O6R I/O7R 42 41 40 39 38 37 36 35 34 33 32 31 7 8 9 10 11 12 13 14 15 16 17 18 , |
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