9

IDT7134SA/LA

High-Speed 4K x 8 Dual-Port Static SRAM

Military, Industrial and Commercial Temperature Ranges

2720 drw 10

R/

VALID

MATCH

VALID

MATCH

NOTES:

1. Write cycle parameters should be adhered to, in order to ensure proper writing.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

NOTES:

1. R/W or CE must be HIGH during all address transitions.

4. During this period, the I/O pins are in the output state, and input signals must not be applied.

6. Timing depends on which enable signal (CE or R/W) is asserted last.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured +500mV from steady state with the Output Test Load

(Figure 2).

CE

2720 drw 11

ADDRESS

R/

W

(7)

(4)

(4)

(2)

OE

(7)

(7)

(3)

(7)