TLK4120

QUAD 0.5 to 1.3 Gbps TRANSCEIVER

SLLS599C − DECEMBER 2003 − REVISED JULY 2006

8

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Terminal Functions

TERMINAL

TYPE

DESCRIPTION

NAME

NO.

TYPE

DESCRIPTION

DINRAP

DINRAN

A6

A7

DINRBP

DINRBN

F17

G17

Input

Serial receive inputs. DINRxP and DINRxN together are the differential serial

DINRCP

DINRCN

P17

R17

Input

Serial receive inputs. DINRxP and DINRxN together are the differential serial

input interface from a copper or an optical I/F module.

DINRDP

DINRDN

U4

U3

DOUTTAP

DOUTTAN

A3

A4

DOUTTBP

DOUTTBN

C17

D17

Output

(high-z

Serial transmit outputs. DOUTTxP and DOUTTxN are differential serial outputs

that interface to copper or an optical I/F module. These terminals transmit NRZ

data at a rate of 20 times the GTx_CLK value. DOUTTxP and DOUTTxN are

DOUTTCP

DOUTTCN

L17

M17

(high-z

power up)

data at a rate of 20 times the GTx_CLK value. DOUTTxP and DOUTTxN are

put in a high-impedance state when LOOPENx is high and are active when

LOOPENx is low. During power-on reset these terminals are high impedance.

DOUTTDP

DOUTTDN

U7

U6

LOOPENx is low. During power-on reset these terminals are high impedance.

ENABLEA

H5

Device enable. When this terminal is held low, the device is placed in

ENABLEB

E10

Input

Device enable. When this terminal is held low, the device is placed in

power-down mode. When asserted high while the device is in power-down

ENABLEC

M9

Input

(w/pullup)

power-down mode. When asserted high while the device is in power-down

mode, the transceiver goes into power on reset before beginning normal

operation.

ENABLED

J6

(w/pullup)

mode, the transceiver goes into power on reset before beginning normal

operation.

GTA_CLK

E2

Reference clock. GTx_CLK is a continuous external input clock that

synchronizes the transmitter interface TDx. The frequency range of GTx_CLK

GTB_CLK

B13

Input

Reference clock. GTx_CLK is a continuous external input clock that

synchronizes the transmitter interface TDx. The frequency range of GTx_CLK

is 25 MHz to 65 MHz.

GTC_CLK

K13

Input

is 25 MHz to 65 MHz.

The transmitter uses the rising edge of this clock to register the 18-bit input

GTD_CLK

P8

The transmitter uses the rising edge of this clock to register the 18-bit input

data (TDx) for serialization.

SYNCA

F4

Fast synchronization. When asserted high, the transmitter substitutes the

SYNCB

D12

Input

Fast synchronization. When asserted high, the transmitter substitutes the

18-bit pattern 111111111000000000 so that when the start/stop bits are framed

SYNCC

N10

Input

(w/pulldown)

18-bit pattern 111111111000000000 so that when the start/stop bits are framed

around the data the receiver can immediately detect the proper deserialization

boundary. This is typically used during initialization of the serial link.

SYNCD

K5

(w/pulldown)

around the data the receiver can immediately detect the proper deserialization

boundary. This is typically used during initialization of the serial link.

LOOPENA

H4

Loop enable. When LOOPENx is active high, the internal loop-back path is

activated. The transmitted serial data is directly routed internally to the inputs

LOOPENB

D10

Input

Loop enable. When LOOPENx is active high, the internal loop-back path is

activated. The transmitted serial data is directly routed internally to the inputs

of the receiver. This provides a self-test capability in conjunction with the

LOOPENC

P12

Input

(w/pulldown)

of the receiver. This provides a self-test capability in conjunction with the

protocol device. The DOUTTxP and DOUTTxN outputs are held in a high

impedance state during the loop-back test. LOOPENx is held low during

LOOPEND

M4

impedance state during the loop-back test. LOOPENx is held low during

standard operational state with external serial outputs and inputs active.

LOCKBA

G5

Receiver lock. When asserted low indicates that the receiver has acquired bit

LOCKBB

E11

Output

Receiver lock. When asserted low indicates that the receiver has acquired bit

synchronization on the data stream and has located the start/stop bits so that

LOCKBC

N9

Output

synchronization on the data stream and has located the start/stop bits so that

the deserialized data presented on the parallel receive bus is properly

received.

LOCKBD

L4

the deserialized data presented on the parallel receive bus is properly

received.

PREEMPHA

A5

Pre-emphasis. When asserted, the serial transmit outputs have extra output

PREEMPHB

E17

Input

Pre-emphasis. When asserted, the serial transmit outputs have extra output

swings on the first bit of any run length of save value bits. If the run length of

PREEMPHC

N17

Input

swings on the first bit of any run length of save value bits. If the run length of

output bits is one, then that bit has larger output swings.

PREEMPHD

U5

output bits is one, then that bit has larger output swings.