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IDT7134SA45L48 Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT7134SA45L48 Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 11 page IDT7134SA/LA High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges 6 NOTES: 1. Transition is measured ±500mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. 'X' in part number indicates power rating (SA or LA). 4. Industrial temperature: for other speeds, packages and powers contact your sales office. AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(3,4) 7134X20 Com'l Only 7134X25 Com'l & Military 7134X35 Com'l & Military Unit Symbol Parameter Min.Max.Min. Max.Min. Max. READ CYCLE tRC Read Cycle Time 20 ____ 25 ____ 35 ____ ns tAA Address Access Time ____ 20 ____ 25 ____ 35 ns tACE Chip Enable Access Time ____ 20 ____ 25 ____ 35 ns tAOE Output Enable Access Time ____ 15 ____ 15 ____ 20 ns tOH Output Hold from Address Change 0 ____ 0 ____ 0 ____ ns tLZ Output Low-Z Time (1,2) 0 ____ 0 ____ 0 ____ ns tHZ Output High-Z Time (1,2) ____ 15 ____ 15 ____ 20 ns tPU Chip Enable to Power Up Time (2) 0 ____ 0 ____ 0 ____ ns tPD Chip Disable to Power Down Time (2) ____ 20 ____ 25 ____ 35 ns 2720 tbl 09a 7134X45 Com'l & Military 7134X55 Com'l, Ind & Military 7134X70 Com'l & Military Unit Symbol Parameter Min.Max.Min.Max. Min. Max. READ CYCLE tRC Read Cycle Time 45 ____ 55 ____ 70 ____ ns tAA Address Access Time ____ 45 ____ 55 ____ 70 ns tACE Chip Enable Access Time ____ 45 ____ 55 ____ 70 ns tAOE Output Enable Access Time ____ 25 ____ 30 ____ 40 ns tOH Output Hold from Address Change 0 ____ 0 ____ 0 ____ ns tLZ Output Low-Z Time (1,2) 5 ____ 5 ____ 5 ____ ns tHZ Output High-Z Time (1,2) ____ 20 ____ 25 ____ 30 ns tPU Chip Enable to Power Up Time (2) 0 ____ 0 ____ 0 ____ ns tPD Chip Disable to Power Down Time (2) ____ 45 ____ 50 ____ 50 ns 2720 tbl 09b |
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