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FWIXEPED0QE000 Datasheet(PDF) 4 Page - Intel Corporation

Part # FWIXEPED0QE000
Description  Advanced 8-Port 10/100 Mbps PHY Transceivers
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

FWIXEPED0QE000 Datasheet(HTML) 4 Page - Intel Corporation

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Contents
4
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
4.3.7
MDIO Management Interface .............................................................................. 121
4.3.8
MII Sectionalization.............................................................................................. 123
4.3.9
MII Interrupts........................................................................................................ 123
4.3.10 Global Hardware Control Interface ...................................................................... 124
4.3.11 FIFO Initial Fill Values.......................................................................................... 124
4.4
Operating Requirements................................................................................................... 125
4.4.1
Power Requirements ........................................................................................... 125
4.4.2
Clock/SYNC Requirements ................................................................................. 125
4.4.2.1
Reference Clock .................................................................................. 125
4.4.2.2
TxCLK Signal (SS-SMII only)............................................................... 125
4.4.2.3
TxSYNC Signal (SMII/SS-SMII)........................................................... 125
4.4.2.4
RxSYNC Signal (SS-SMII only) ........................................................... 125
4.4.2.5
RxCLK Signal (SS-SMII only) .............................................................. 126
4.5
Initialization ....................................................................................................................... 126
4.5.1
MDIO Control Mode............................................................................................. 126
4.5.2
Hardware Control Mode....................................................................................... 126
4.5.3
Power-Down Mode .............................................................................................. 127
4.5.3.1
Global (Hardware) Power Down .......................................................... 128
4.5.3.2
Port (Software) Power Down ............................................................... 128
4.5.4
Reset ................................................................................................................... 128
4.5.5
Hardware Configuration Settings......................................................................... 129
4.6
Link Establishment............................................................................................................ 129
4.6.1
Auto-Negotiation .................................................................................................. 129
4.6.1.1
Base Page Exchange .......................................................................... 129
4.6.1.2
Manual Next Page Exchange .............................................................. 130
4.6.1.3
Controlling Auto-Negotiation ................................................................ 130
4.6.1.4
Link Criteria.......................................................................................... 130
4.6.1.5
Parallel Detection................................................................................. 131
4.6.1.6
Reliable Link Establishment While Auto MDI/MDIX is
Enabled in Forced Speed Mode .......................................................... 131
4.7
Serial MII Operation.......................................................................................................... 132
4.7.1
SMII Reference Clock.......................................................................................... 135
4.7.2
TxSYNC Pulse (SMII/SS-SMII)............................................................................ 135
4.7.3
Transmit Data Stream.......................................................................................... 135
4.7.3.1
Transmit Enable................................................................................... 135
4.7.3.2
Transmit Error ...................................................................................... 135
4.7.4
Receive Data Stream........................................................................................... 136
4.7.4.1
Carrier Sense....................................................................................... 136
4.7.4.2
Receive Data Valid .............................................................................. 136
4.7.4.3
Receive Error ....................................................................................... 136
4.7.4.4
Receive Status Encoding..................................................................... 136
4.7.5
Collision ............................................................................................................... 136
4.7.6
Source Synchronous-Serial Media Independent Interface .................................. 137
4.8
RMII Operation ................................................................................................................. 141
4.8.1
RMII Reference Clock.......................................................................................... 141
4.8.2
Transmit Enable................................................................................................... 142
4.8.3
Carrier Sense & Data Valid.................................................................................. 142
4.8.4
Receive Error....................................................................................................... 142
4.8.5
Out-of-Band Signaling ......................................................................................... 142
4.8.6
4B/5B Coding Operations .................................................................................... 142
4.9
100 Mbps Operation ......................................................................................................... 145


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