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STSMIA832 Datasheet(PDF) 8 Page - STMicroelectronics

Part # STSMIA832
Description  1.8V/2.8V High speed dual differential line receivers, standard mobile imaging architecture (SMIA) decoder deserializer
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STSMIA832 Datasheet(HTML) 8 Page - STMicroelectronics

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Pin configuration
STSMIA832
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Frame synchronization
Each image frame begins with frame start synchronization code (SOF) and ends with frame
end synchronization code (EOF). Each line inside the frame begins with line start
synchronization code (SOL) and ends with line end synchronization code (EOL). The period
between EOL code and new SOL code is called line blanking period. Similarly, the time
between EOF code and new SOF code is called frame blanking period. The total size of one
image frame shall be a multiple of 128 bits.
In the beginning of frame and in the end of frame, line synchronization codes are replaced
by the frame synchronization codes. Synchronization signal usage is shown in Figure 4
below. Bit order of the synchronization codes is the same as for data, byte-wise LSB first.
The purpose of logical channels is to separate different data flows, which are interleaved in
the data stream.
The DMA channel identifier number is directly encoded in the 4-byte CCP embedded sync
codes. The CCP receiver will monitor the DMA channel identifier and de-multiplex the
interleaved video streams to their appropriate DMA channel. A maximum of 8 data streams
is supported. Valid channel identifiers are 0 to 7.
X = channel number 0 to 7.
Figure 7.
CCP2 Synchronization codes
Table 2.
Synchronization codes as per SMIA specifications
Name
Synchronization Codes
Notes
SOL
FFH 00H 00H X0H
Line Start Code
EOL
FFH 00H 00H X1H
Line End Code
SOF
FFH 00H 00H X2H
Frame Start Code
EOF
FFH 00H 00H X3H
Frame End Code
Logical Channels
FFH 00H 00H 0XH (to) FFH 00H 00H 7XH
DMA Channel Identifier from Channel 0 to 7


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