128K x 32 Synchronous-Flow-Through 3.3V Cache RAM
CY7C1338
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
May 5, 2000
Features
• Supports 117-MHz microprocessor cache systems with
zero wait states
• 128K by 32 common I/O
• Fast clock-to-output times
— 7.5 ns (117-MHz version)
• Two-bit wraparound counter supporting either inter-
leaved or linear burst sequence
• Separate processor and controller address strobes pro-
vide direct interface with the processor and external
cache controller
• Synchronous self-timed write
• Asynchronous output enable
•3.3V I/Os
• JEDEC-standard pinout
• 100-pin TQFP packaging
• ZZ “sleep” mode
Functional Description
The CY7C1338 is a 3.3V, 128K by 32 synchronous cache
RAM designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access delay from clock
rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap-
tures the first address in a burst and increments the address
automatically for the rest of the burst access.
The CY7C1338 allows both interleaved and linear burst se-
quences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address
Strobe (ADSC) inputs. Address advancement is controlled by
the address advancement (ADV) input.
A synchronous self-timed write mechanism is provided to sim-
plify the write interface. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.
Selection Guide
7C1338-117
7C1338-100
7C1338-90
7C1338-50
Maximum Access Time (ns)
7.5
8.0
8.5
11.0
Maximum Operating Current (mA)
350
325
300
250
Maximum Standby Current (mA)
2.0
2.0
2.0
2.0
Intel and Pentium are registered trademarks of Intel Corporation.
CLK
ADV
ADSC
A[16:0]
GW
BWE
BW
0
CE1
CE3
CE2
OE
ZZ
BURST
COUNTER
DQ[31:24]
BYTEWRITE
REGISTERS
ADDRESS
REGISTER
D
Q
INPUT
REGISTERS
128K X 32
MEMORY
ARRAY
CLK
Q0
Q1
Q
D
CE
CE
CLR
SLEEP
CONTROL
DQ[23:16]
BYTEWRITE
REGISTERS
D
Q
DQ
DQ[15:8]
BYTEWRITE
REGISTERS
DQ[7:0]
BYTEWRITE
REGISTERS
D
Q
ENABLE
REGISTER
D
Q
CE
CLK
32
32
17
15
15
17
(A0,A1) 2
MODE
ADSP
Logic Block Diagram
DQ[31:0]
BW
1
BW
2
BW
3
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