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PPC5567MVZ112R2 Datasheet(PDF) 11 Page - Freescale Semiconductor, Inc |
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PPC5567MVZ112R2 Datasheet(HTML) 11 Page - Freescale Semiconductor, Inc |
11 / 56 page Electrical Characteristics MPC5567 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice Freescale Semiconductor 11 Although there is no power sequencing required between VRC33 and VDDSYN during power up, for the VRC stage turn-on to operate within specification, VRC33 must not lead VDDSYN by more than 600 mV or lag by more than 100 mV. Higher spikes in the emitter current of the pass transistor will occur if VRC33 leads or lags VDDSYN by more than these amounts. The value of that higher spike in current depends on the board power supply circuitry and the amount of board level capacitance. Furthermore, when all of the PORs negate, the system clock will start to toggle, adding another large increase of the current consumption from VRC33. If VRC33 lags VDDSYN by more than 100 mV, this increased current consumption can drop VDD low enough to assert the 1.5-V POR again. Oscillations are even possible because when the 1.5-V POR asserts, the system clock stops, causing the voltage on VDD to rise until the 1.5-V POR negates again. Any oscillations stop when VRC33 is powered sufficiently. When powering down, VRC33 and VDDSYN do not have a delta requirement to each other, because the bypass capacitors internal and external to the device are already charged. When not powering up or down, VRC33 and VDDSYN do not have a delta requirement to each other for the VRC to operate within specification. Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, etc., the state of the I/O pins during power up/down varies depending on power. Table 7 gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type), and Table 8 for all pins with pad type pad_mh (medium type) and pad_sh (slow type). 3.7.1 Power Up Sequence (If VRC33 Grounded) In this case, the 1.5-V VDD supply must rise to 1.35-V before the 3.3-V VDDSYN and the RESET power supplies rises above 2.0 V. This ensures that digital logic in the PLL on the 1.5-V supply will not begin to operate below the specified operation range lower limit of 1.35 V. Since the internal 1.5-V POR is disabled, Table 7. Power Sequence Pin States (Fast Pads) VDDE VDD33 VDD pad_fc (Fast) Output Driver State Comment LOW X X Low Functional I/O pins are clamped to VSS and VDDE VDDE LOW X High VDDE VDD33 LOW High Impedance POR asserted. VDDE VDD33 VDD Functional No POR asserted Table 8. Power Sequence Pin States (Medium and Slow Pads) VDDEH VDD pad_mh/pad_sh (Medium and Slow) Output Driver Comment LOW X Low Functional I/O pins are clamped to VSS and VDDEH VDDEH LOW High Impedance POR asserted VDDEH VDD Functional No POR asserted |
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