10 / 22 page
10
SX061
1Mbit/s DQPSK/DBPSK
Digital Demodulator
WavePlex
™
User’s Manual
Table 2:
The output of the VCO is divided again by a second
divider, which can divide by 1, 2, 4, 8 or 16. This can be
programmed
using
the
div1-16
register
of
the
programming string as listed below.
Table 3:
The AD Converter
The AD converter discerns three levels: 1, 0, and –1. The
AD conversion is accomplished by using a window
comparator.
The output of the window comparator defines the three
levels. The window comparator is latched on the internal
(sample) clock of the SX061. This sample clock can run
at frequencies up to 100 MHz.
The input signal has to be capacatively coupled to the
RX_IN pin (appr. 10nF). The input resistance of the AD-
converter is 200k, the DC level is 2.1 V.
DIV25_50
FVCO/Fref
525
630
735
840
945
10
50
DIV1_16
FVCO/Fclk
01
12
24
38
416
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
