amplifier will operate with R

Ω, how-

ever results may be substantially different than predicted

from ideal models. In particular the voltage potential be-

tween the Inverting and Non-Inverting inputs cannot be ex-

pected to remain small.

Inverting gain applications that require impedance matched

inputs may limit gain flexibility somewhat (especially if maxi-

mum bandwidth is required). The impedance seen by the

source is R

/Gain. Thus for a SOT23 in a gain of — 5V/V, an R

Ω

is optimum and R

Ω. Without a termination resistor,

R

Ω. Using an R

T

of 109

Ω will set the input resistance to match a 50Ω source.

Note that source impedances greater then R

matched in the inverting configuration.

For more information see Application Note OA-13 which

describes the relationship between R

quency response for current feedback operational amplifiers.

The value for the inverting input impedance for the LMH6703

is approximately 30

Ω. The LMH6703 is designed for opti-

mum performance at gains of +1 to +10 V/V and −1 to −9

V/V. Higher gain configurations are still useful, however, the

bandwidth will fall as gain is increased, much like a typical

voltage feedback amplifier.

The LMH6703 data sheet shows both SOT23-6 and SOIC

data in the Electrical Characteristic section to aid in selecting

the right package. The Typical Performance Characteristics

section shows SOT23-6 package plots only.

CAPACITIVE LOAD DRIVE

Capacitive output loading applications will benefit from the

use of a series output resistor R

of a series output resistor, R

output under capacitive loading. Capacitive loads from 5 to

120 pF are the most critical, causing ringing, frequency

response peaking and possible oscillation. The chart “Sug-

gested R

selecting a series output resistor for mitigating capacitive

loads. The values suggested in the charts are selected for

0.5 dB or less of peaking in the frequency response. This

produces a good compromise between settling time and

bandwidth. For applications where maximum frequency re-

sponse is needed and some peaking is tolerable, the value

of R

values.

DC ACCURACY AND NOISE

Example below shows the output offset computation equa-

tion for the non-inverting configuration (see Figure 1) using

the typical bias current and offset specifications for A

Output Offset : V

Where R

inverting input.

Example computation for A

Ω,R

Ω:

V

−3.7 mV to 4.5 mV

A good design, however, should include a worst case calcu-

lation using Min/Max numbers in the data sheet tables, in

order to ensure "worst case" operation.

Further improvement in the output offset voltage and drift is

possible using the composite amplifiers described in Appli-

cation Note OA-7. The two input bias currents are physically

unrelated in both magnitude and polarity for the current

feedback topology. It is not possible, therefore, to cancel

their effects by matching the source impedance for the two

inputs (as is commonly done for matched input bias current

devices).

The total output noise is computed in a similar fashion to the

output offset voltage. Using the input noise voltage and the

two input noise currents, the output noise is developed

through the same gain equations for each term but com-

bined as the square root of the sum of squared contributing

elements. See Application Note OA-12 for a full discussion of

noise calculations for current feedback amplifiers.

PRINTED CIRCUIT LAYOUT

Whenever questions about layout arise, use the evaluation

board as a guide. The CLC730216 is the evaluation board

supplied with SOT23-6 samples of the LMH6703 and the

CLC730227 is the evaluation board supplied with SOIC

samples of the LMH6703.

To reduce parasitic capacitances, ground and power planes

should be removed near the input and output pins. Compo-

nents in the feedback path should be placed as close to the

device as possible to minimize parasitic capacitance. For

long signal paths controlled impedance lines should be

used, along with impedance matching elements at both

ends.

Bypass capacitors should be placed as close to the device

as possible. Bypass capacitors from each voltage rail to

ground are applied in pairs. The larger electrolytic bypass

capacitors can be located further from the device, the

smaller ceramic bypass capacitors should be placed as

close to the device as possible. In Figure 1 and Figure 2 C

SS

is optional, but is recommended for best second order har-

monic distortion.

20110635

FIGURE 4. Decoupling Capacitive Loads

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