BQ4024MA-120 datasheet(7/12 Pages) ETC1

Part #	BQ4024MA-120

Description	128Kx16 Nonvolatile SRAM

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7 / 12 page

7

Sept. 1992

Write Cycle No. 1 (WE-Controlled)

1,2,3

Write Cycle No. 2 (CE-Controlled)

1,2,3,4,5

Notes:

1.

CE or WE must be high during address transition.

2.

Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the

outputs must not be applied.

3.

If OE is high, the I/O pins remain in a state of high impedance.

4.

Either tWR1 or tWR2 must be met.

5.

Either tDH1 or tDH2 must be met.

bq4024/bq4024Y

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