NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
REV 1.0
May, 2001
6
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Power On and Initialization
The default power on state of the mode register is supplier specific and may be undefined. The following power on and initializa-
tion sequence guarantees the device is preconditioned to each users specific needs.
Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During power
on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the “NOP”
state. The power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. The CK signal must be started
at the same time. After power on, an initial pause of 200
µs is required followed by a precharge of all banks using the precharge
command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high
during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to ini-
tialize the Mode Register. A minimum of two Auto Refresh cycles (CBR) are also required. These may be done before or after
programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes.
Programming the Mode Register
For application flexibility, CAS latency, burst length, burst sequence, and operation type are user defined variables and must be
programmed into the SDRAM Mode Register with a single Mode Register Set Command. Any content of the Mode Register can
be altered by re-executing the Mode Register Set Command. If the user chooses to modify only a subset of the Mode Register
variables, all four variables must be redefined when the Mode Register Set Command is issued.
After initial power up, the Mode Register Set Command must be issued before read or write cycles may begin. All banks must
be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The
Mode Register Set Command is activated by the low signals of RAS, CAS, CS, and WE at the positive edge of the clock. The
address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new
command may be issued following the mode register set command once a delay equal to tRSC has elapsed.
CAS Latency
The CAS latency is a parameter that is used to define the delay from when a Read Command is registered on a rising clock
edge to when the data from that Read Command becomes available at the outputs. The CAS latency is expressed in terms of
clock cycles and can have a value of 2 or 3 cycles. The value of the CAS latency is determined by the speed grade of the
device and the clock frequency that is used in the application. A table showing the relationship between the CAS latency, speed
grade, and clock frequency appears in the Electrical Characteristics section of this document. Once the appropriate CAS
latency has been selected it must be programmed into the mode register after power up, for an explanation of this procedure
see Programming the Mode Register in the previous section.
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