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MC74HC299N Datasheet(PDF) 5 Page - Motorola, Inc |
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MC74HC299N Datasheet(HTML) 5 Page - Motorola, Inc |
5 / 8 page MC74HC299 High–Speed CMOS Logic Data DL129 — Rev 6 3–5 MOTOROLA FUNCTION TABLE Inputs Response Mode Reset Mode Select Output Enables Clock Serial Inputs PA/QA PB/QB PC/QC PD/QD PE/QE PF/QF PG/QG PH/QH QA′ QH′ Mode Reset S2 S1 OE1† OE2† Clock DA DH PA/QA PB/QB PC/QC PD/QD PE/QE PF/QF PG/QG PH/QH QA′ QH′ Reset L X L L L X X X L L L L L L L L L L L L X L L X X X L L L L L L L L L L L H H X X X X X QA through QH = Z L L Shift Right H L H H X D X Shift Right: QA through QH = Z; DA ³ FA; FA ³ FB; etc. D QG Right H L H X H D X Shift Right: QA through QH = Z; DA ³ FA; FA ³ FB; etc. D QG H L H L L D X Shift Right: DA ³ FA = QA; FA ³ FB = QB; etc. D QG Shift Left H H L H X X D Shift Left: QA through QH = Z; DH ³ FH; FH ³ FG; etc. QB D Left H H L X H X D Shift Left: QA through QH = Z; DH ³ FH; FH ³ FG; etc. QB D H H L L L X D Shift Left: DH ³ FH = QH; FH ³ FG = QG; etc. QB D Parallel Load H H H X X X X Parallel Load: PN ³ FN PA PH Hold H L L H X X X X Hold: QA through QH = Z; FN = FN PA PH H L L X H X X X Hold: QA through QH = Z; FN = FN PA PH H L L L L X X X Hold: QN = QN PA PH Z = high impedance D = data on serial input F = flip–flop (see Logic Diagram) †When one or both output controls are high the eight input/output terminals are disabled to the high impedance state, however, sequential operation or clearing of the register is not affected. PIN DESCRIPTIONS DATA INPUTS SA (Pin 11) Serial data input (Shift Right). Data on this input is shifted into the shift register on the rising edge of Clock when S2 is low and S1 is high (shift right mode). SH (Pin 18) Serial data input (Shift Left). Data on this input is shifted into the shift register on the rising edge of Clock when S2 is high and S1 is low (shift left mode). PA through PH (Pins 7, 13, 6, 14, 5, 15, 4, 16) Parallel data port inputs. Data on these pins can be paral- lel loaded into the shift register on the rising edge of Clock when both S1 and S2 are high. For any other combination of S1 and S2, these pins serve as the outputs of the shift register. CONTROL INPUTS Clock (Pin 12) Clock input. A low–to–high transition on this pin shifts the data at each stage to the next stage (shift right or left mode) or loads the data at the parallel data inputs into the shift reg- ister (parallel load mode). OE1, OE2 (Pins 2, 3) Active–low output enables. When both OE1 and OE2 are low, the Outputs QA through QH are enabled. When one or both output enables are high, the outputs are forced to the high–impedance state; however, sequential operation or clearing of the register is not affected. Reset (Pin 9) Active–low reset. A low on this pin resets all stages of the register to a low level. The reset operation is asynchronous. S1, S2 (Pins 1, 19) Mode select inputs. The levels present at these pins deter- mine the shift register’s mode of operation: S1 = S2 = Low. Hold. S1 = Low, S2 High. Shift left. S1 = High, S2 Low. Shift right. S1 = S2 = High. Parallel load. OUTPUTS QA′, QH′ (Pins 8, 17) Serial data outputs. These are the outputs of the first and last stages of the shift register, respectively. These outputs are not 3–state outputs and have standard drive capabilities. QA through QH (Pins 7, 13, 6, 14, 5, 15, 4, 16) Parallel data port outputs. Shifted data is present at these pins when OE1 and OE2 are low. For all other combinations of OE1 and OE2 these outputs are in the high–impedance state. |
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