9
FS6131-01
FS6131-01
FS6131-01
FS6131-01
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
5.0
I
2C-bus Control Interface
This device is a read/write slave device
meeting
all
Philips
I
2C-bus specifications
except a “general call.” The bus has to be
controlled by a master device that generates
the serial clock SCL, controls bus access, and generates
the START and STOP conditions while the device works
as a slave. Both master and slave can operate as a
transmitter or receiver, but the master device determines
which mode is activated. A device that sends data onto
the bus is defined as the transmitter, and a device re-
ceiving data as the receiver.
I
2C-bus logic levels noted herein are based on a percent-
age of the power supply (VDD). A logic-one corresponds
to a nominal voltage of VDD, while a logic-zero corre-
sponds to ground (VSS).
5.1
Bus Conditions
Data transfer on the bus can only be initiated when the
bus is not busy. During the data transfer, the data line
(SDA) must remain stable whenever the clock line (SCL)
is high. Changes in the data line while the clock line is
high will be interpreted by the device as a START or
STOP condition. The following bus conditions are defined
by the I
2C-bus protocol.
5.1.1
Not Busy
Both the data (SDA) and clock (SCL) lines remain high to
indicate the bus is not busy.
5.1.2
START Data Transfer
A high to low transition of the SDA line while the SCL in-
put is high indicates a START condition. All commands to
the device must be preceded by a START condition.
5.1.3
STOP Data Transfer
A low to high transition of the SDA line while SCL is held
high indicates a STOP condition. All commands to the
device must be followed by a STOP condition.
5.1.4
Data Valid
The state of the SDA line represents valid data if the SDA
line is stable for the duration of the high period of the SCL
line after a START condition occurs. The data on the
SDA line must be changed only during the low period of
the SCL signal. There is one clock pulse per data bit.
Each data transfer is initiated by a START condition and
terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions
is determined by the master device, and can continue
indefinitely. However, data that is overwritten to the de-
vice after the first eight bytes will overflow into the first
register, then the second, and so on, in a first-in, first-
overwritten fashion.
5.1.5
Acknowledge
When addressed, the receiving device is required to gen-
erate an Acknowledge after each byte is received. The
master device must generate an extra clock pulse to co-
incide with the Acknowledge bit. The acknowledging de-
vice must pull the SDA line low during the high period of
the master acknowledge clock pulse. Setup and hold
times must be taken into account.
The master must signal an end of data to the slave by not
generating and acknowledge bit on the last byte that has
been read (clocked) out of the slave. In this case, the
slave must leave the SDA line high to enable the master
to generate a STOP condition.
5.2
I
2C-bus Operation
All programmable registers can be accessed randomly or
sequentially via this bi-directional two wire digital inter-
face. The crystal oscillator does not have to run for com-
munication to occur.
The device accepts the following I
2C-bus commands:
5.2.1
Slave Address
After generating a START condition, the bus master
broadcasts a seven-bit slave address followed by a R/W
bit. The address of the device is:
A6
A5
A4
A3
A2
A1
A0
101
1
X
00
where X is controlled by the logic level at the ADDR pin.
The variable ADDR bit allows two different FS6131 de-
vices to exist on the same bus. Note that every device on
an I
2C-bus must have a unique address to avoid bus
conflicts. The default address sets A2 to 0 via the pull-
down on the ADDR pin.
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