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GTLPH1612 Datasheet(PDF) 8 Page - Texas Instruments |
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GTLPH1612 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 15 page  www.ti.com Live-Insertion Specifications for B Port Timing Requirements SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D – OCTOBER 1999 – REVISED MAY 2005 over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN MAX UNIT Ioff VCC = 0, BIAS VCC = 0, VI or VO = 0 to 1.5 V 10 µA IOZPU VCC = 0 to 1.5 V, BIAS VCC = 0, VO = 0.5 V to 1.5 V, OE = 0 ±30 µA IOZPD VCC = 1.5 V to 0, BIAS VCC = 0, VO = 0.5 V to 1.5 V, OE = 0 ±30 µA VCC = 0 to 3.15 V 5 mA ICC (BIAS VCC) BIAS VCC = 3.15 V to 3.45 V, VO (B port) = 0 to 1.5 V VCC = 3.15 V to 3.45 V 10 µA VO VCC = 0, BIAS VCC = 3.3 V, IO = 0 0.95 1.05 V IO VCC = 0, BIAS VCC = 3.15 V to 3.45 V, VO (B port) = 0.6 V –1 µA over recommended ranges of supply voltage and operating free-air temperature, V TT = 1.5 V and VREF = 1 V for GTLP (normal mode) (unless otherwise noted) MIN MAX UNIT fclock Clock frequency 175 MHz LEAB or LEBA high 3 tw Pulse duration ns CLKAB or CLKBA high or low 3 A before CLKAB ↑ 2.2 B before CLKBA ↑ 2.4 A before LEAB ↓, CLK = Don't care 1.8 tsu Setup time ns B before LEBA ↓, CLK = Don't care 2.1 CEAB before CLKAB ↑ 1.5 CEBA before CLKBA ↑ 1.5 A after CLKAB ↑ 0.7 B after CLKBA ↑ 0.5 A after LEAB ↓, CLK = Don't care 1.2 th Hold time ns B after LEBA ↓, CLK = Don't care 0.9 CEAB after CLKAB ↑ 1.5 CEBA after CLKBA ↑ 1.5 8 |
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