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AD9237BCPZRL7-40 Datasheet(PDF) 8 Page - Analog Devices |
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AD9237BCPZRL7-40 Datasheet(HTML) 8 Page - Analog Devices |
8 / 28 page AD9237 Rev. 0 | Page 8 of 28 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DNC = DO NOT CONNECT PIN 1 INDICATOR 1 MODE2 2 CLK 3 OE 4 PDWN 5 GC 6 DNC 7 D0 (LSB) 8 D1 24 VREF 23 SENSE 22 MODE 21 OTR 20 D11 (MSB) 19 D10 18 D9 17 D8 TOP VIEW (Not to Scale) AD9237 Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin Number Mnemonic Description 1 MODE2 SHA Gain Select and Power Scaling Control (see Table 8). 2 CLK Clock Input Pin. 3 OE Output Enable Pin (Active Low). 4 PDWN Power-Down Function Selection (see Table 9). 5 GC Gray Code Control (Active High). 6 DNC Do Not Connect. 7 to 14, 17 to 20 D0 (LSB) to D11 (MSB) Data Output Bits. 15 DGND Digital Output Ground. 16 DRVDD Digital Output Driver Supply. Must be decoupled to DGND with a minimum 0.1 μF capacitor. Recommended decoupling is 0.1 μF in parallel with 10 μF. 21 OTR Out-of-Range Indicator. 22 MODE Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection (see Table 10). 23 SENSE Reference Mode Selection (see Table 7). 24 VREF Voltage Reference Input/Output (see Table 7). 25 REFB Differential Reference (−). Must be decoupled to REFT with a minimum 10 μF capacitor. 26 REFT Differential Reference (+). 27, 32 AVDD Analog Power Supply. Must be decoupled to AGND with a minimum 0.1 μF capacitor. Recommended decoupling is 0.1 μF in parallel with 10 μF. 28, 31 AGND Analog Ground. 29 VIN+ Analog Input Pin (+). 30 VIN− Analog Input Pin (−). |
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