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AD8106 Datasheet(PDF) 5 Page - Analog Devices |
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AD8106 Datasheet(HTML) 5 Page - Analog Devices |
5 / 28 page AD8106/AD8107 Rev. 0 | Page 5 of 28 TIMING CHARACTERISTICS Table 2. Parameter Limit at TMIN, T Unit Description MAX t1 20 ns min Data setup time t 100 ns min CLK pulse width 2 t 20 ns min Data hold time 3 t 100 ns min CLK pulse separation 4 t5 0 ns min CLK to UPDATE delay t6 50 ns min UPDATE pulse width – 8 ns max Propagation delay, UPDATE to switch on or off – 100 ns max CLK, UPDATE rise and fall times – 200 ns min RESET time 1 0 1 0 1 = LATCHED CLK D0 TO D4 A0 TO A2 0 = TRANSPARENT UPDATE t5 t6 t2 t1 t3 t4 Figure 2. Timing Diagram Table 3. Logic Levels VIH V I IL IH IIL RESET, CLK, D0, D1, D2, D3, D4, A0, A1, A2, CE, UPDATE RESET, CLK, D0, D1, D2, D3, D4, A0, A1, A2, CE, UPDATE RESET, CLK, D0, D1, D2, D3, D4, A0, A1, A2, RESET, CLK, D0, D1, D2, D3, D4, A0, A1, A2, CE, UPDATE CE, UPDATE 2.0 V min 0.8 V max 20 μA max −400 μA min |
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