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SSTUB32866 Datasheet(PDF) 10 Page - NXP Semiconductors

Part # SSTUB32866
Description  1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

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SSTUB32866_2
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 9 October 2006
10 of 29
NXP Semiconductors
SSTUB32866
1.8 V DDR2-800 configurable registered buffer with parity
[1]
PPO0 is the previous state of output PPO; QERR0 is the previous state of output QERR.
[2]
Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.
Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.
Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.
[3]
PAR_IN arrives one clock cycle (C0 = 0), or two clock cycles (C0 = 1), after the data to which it applies.
[4]
This condition assumes QERR is HIGH at the crossing of CK going HIGH and CK going LOW. If QERR is LOW, it stays latched LOW for
two clock cycles or until RESET is driven LOW.
8.
Limiting values
[1]
The input and output negative voltage ratings may be exceeded if the input and output clamping current ratings are observed.
[2]
This value is limited to 2.5 V maximum.
Table 5.
Parity and standby function table
L = LOW voltage level; H = HIGH voltage level; X = don’t care;
↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition.
Inputs
Outputs[1]
RESET
DCS
CSR
CK
CK
∑ of inputs = H
(D1 to D25)
PAR_IN[2]
PPO[3]
QERR[4]
HL
X
↑↓
even
L
L
H
HL
X
↑↓
odd
L
H
L
HL
X
↑↓
even
H
H
L
HL
X
↑↓
odd
H
L
H
HH
L
↑↓
even
L
L
H
HH
L
↑↓
odd
L
H
L
HH
L
↑↓
even
H
H
L
HH
L
↑↓
odd
H
L
H
HH
H
↑↓
X
X
PPO0
QERR0
H
X
X
L or H
L or H
X
X
PPO0
QERR0
L
X or floating
X or floating
X or floating
X or floating
X or floating
X or floating
L
H
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDD
supply voltage
−0.5
+2.5
V
VI
input voltage
receiver
−0.5[1]
+2.5[2]
V
VO
output voltage
driver
−0.5[1]
VDD + 0.5[2]
V
IIK
input clamping current
VI < 0 V or VI >VDD
-
−50
mA
IOK
output clamping current
VO < 0 V or VO >VDD
-
±50
mA
IO
output current
continuous; 0 V < VO < VDD
-
±50
mA
ICCC
continuous current through
each VDD or GND pin
-
±100
mA
Tstg
storage temperature
−65
+150
°C
Vesd
electrostatic discharge
voltage
Human Body Model (HBM); 1.5 k
Ω; 100 pF
2
-
kV
Machine Model (MM); 0
Ω; 200 pF
200
-
V


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