Electronic Components Datasheet Search |
|
IDT72221L15JB Datasheet(PDF) 9 Page - Integrated Device Technology |
|
IDT72221L15JB Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 19 page 5.07 9 IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO ™ 64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES Figure 4. Reset Timing NOTES: 1. Holding WEN2/ LD HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable flag offset registers. 2. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1. 3. The clocks (RCLK, WCLK) can be free-running during reset. tRS tRSR RS REN1, REN2 tRSF tRSF OE = 1 OE = 0 (2) EF, PAE FF, PAF Q0 - Q8 2655 drw 06 WEN2/ LD WEN1 (1) tRSS tRSF tRSR tRSS tRSR tRSS |
Similar Part No. - IDT72221L15JB |
|
Similar Description - IDT72221L15JB |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |