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74F525PCX Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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74F525PCX Datasheet(HTML) 3 Page - National Semiconductor (TI) |
3 / 10 page Functional Description (Continued) Function Table M2 M1 M0 Function 0 0 0 Mode 0 0 0 1 Mode 1 0 1 0 Mode 2 0 1 1 Mode 3 1 0 0 Mode 4 1 0 1 Mode 5 1 1 0 Mode 6 1 1 1 Mode 7 MODE 4 Interval Timer Pulse Output with Count Hold While XTR is HIGH the data in the data latches is loaded into the counter upon the next positive edge of CP The negative edge of XTR enables the count-down to begin with the next positive edge of CP When the count reaches zero Q normally low is brought HIGH for a single period of CP Q2 toggles state on the positive edge of Q Taking XTR HIGH before the counters reach zero stops the count-down from the point where it was held Data cannot be reloaded into the counter until a count of zero is reached See Figure 3 MODE 5 Interval Timer Inverted Pulse Output with Count Hold The operation is exactly the same as Mode 4 except that Q is normally HIGH and goes LOW for a single period of CP Q2 toggles on the negative-edge of Q See Figure 3 MODE 6 Retriggerable Synchronous One-Shot When XTR is HIGH the data in the data latches is loaded into the counter upon the positive edge of CP The negative edge of XTR enables the count-down to begin with the next positive edge of CP wehre Q normally LOW is then brought HIGH and the counter is decremented when the count reaches zero Q is brought LOW and Q2 is toggled Bringing XTR HIGH during the count-down will allow the data in the data latches to be loaded into the counter with the next positive edge of CP but will not affect Q See Fig- ure 4 NOTE that the pulse width of Q will be N-1 clock cycles where N is the number loaded into the counter Ne1 should not be used as this may cause unpredictable results MODE 7 Frequency Generator When XTR is HIGH the data in the data latches is loaded into the counter upon the positive edge of CP The negative edge of XTR enables the count-down to begin with the next positive edge of CP When the count reaches zero Q nor- mally LOW is brought HIGH for a single period of CP and Q2 is toggled The same clock edge that brings Q HIGH also loads the data in the data latches into the counter The counter will start to count on the next positive edge of CP This mode will run continuously after an initial XTR until stopped by MR Taking XTR HIGH at any time causes the data in the data latches to be loaded into the counter and Q output to be cleared with the next positive edge of CP See Figure 5 Block Diagram TLF9547 – 4 3 |
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