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74AUP2G00_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 01 — 25 August 2006 2 of 16 Philips Semiconductors 74AUP2G00 Low-power dual 2-input NAND gate 3. Ordering information 4. Marking 5. Functional diagram 6. Pinning information 6.1 Pinning Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP2G00DC −40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 74AUP2G00GT −40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads; 8 terminals; body 1 × 1.95 × 0.5 mm SOT833-1 74AUP2G00GM −40 °C to +125 °C XQFN8 plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 × 1.6 × 0.5 mm SOT902-1 Table 2. Marking Type number Marking code 74AUP2G00DC p00 74AUP2G00GT p00 74AUP2G00GM p00 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) mna712 1A 1B 1Y 2 1 7 2A 2B 2Y 6 5 3 mna713 7 & & 2 1 3 6 5 mna099 B A Y Fig 4. Pin configuration SOT765-1 (VSSOP8) 74AUP2G00 1A VCC 1B 1Y 2Y 2B GND 2A 001aae362 1 2 3 4 6 5 8 7 |
