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IDT72841L25PF Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT72841L25PF Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 21 page  5.15 10 COMMERCIAL TEMPERATURE 72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO ™ 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 Figure 5. Write Cycle Timing tDH tENH tSKEW1 (1) tCLK tCLKH tCLKL tDS tENS tWFF tWFF WCLKA (WCLKB) (DA0 - DA8 DB0 - DB8) WENA1 ( WENB1) WENA2 (WENB2) (If Applicable) FFA ( FFB) RCLKA (RCLKB) RENA1, RENA2 ( RENB1, RENB2) NO OPERATION NO OPERATION 3034 drw 07 DATA IN VALID NOTE: 1. tSKEW1 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for FFA (FFB) to change during the current clock cycle. If the time between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then FFA (FFB) may not change state until the next WCLKA (WCLKB) edge. |
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