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IDT72821L25PF Datasheet(PDF) 7 Page - Integrated Device Technology

Part # IDT72821L25PF
Description  DUAL CMOS SyncFIFO
Download  21 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72821L25PF Datasheet(HTML) 7 Page - Integrated Device Technology

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COMMERCIAL TEMPERATURE
72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
LDA WENA1 WCLKA(1)
OPERATION ON FIFO A
LDB WENB1 WCLKB(1)
OPERATION ON FIFO B
0
0
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0
1
No Operation
1
0
Write Into FIFO
1
1
No Operation
NOTE:
3034 drw 04
1. The same selection sequence applies to reading from the registers.
RENA1 and RENA2 (RENB1 and RENB2) are enabled and read is per-
formed on the LOW-to-HIGH transition of RCLKA (RCLKB).
Figure 3. Offset Register Formats and Default Values for the A and B FIFOs
If FIFO A (B) is configured to have programmable flags,
when the
WENA1 (WENB1) and WENA2/LDA (WENB2/LDB)
are set LOW, data on the DA (DB) inputs are written into the
Empty (Least Significant Bit) offset register on the first LOW-
to-HIGH transition of the WCLKA (WCLKB). Data are written
into the Empty (Most Significant Bit) offset register on the
second LOW-to-HIGH transition of WCLKA (WCLKB), into
the Full (Least Significant Bit) offset register on the third
transition, and into the Full (Most Significant Bit) offset register
on the fourth transition. The fifth transition of WCLKA (WCLKB)
again writes to the Empty (Least Significant Bit) offset register.
However, writing all offset registers does not have to occur
at one time. One or two offset registers can be written and then
by bringing
LDA (LDB) HIGH, FIFO A (B) is returned to normal
read/write operation. When
LDA(LDB)issetLOW,and WENA1
(
WENB1) is LOW, the next offset register in sequence is
written.
The contents of the offset registers can be read on the QA
(QB) outputs when WENA2/
LDA (WENB2/LDB) is set LOW
and both Read Enables
RENA1, RENA2 (RENB1, RENB2) are
set LOW. Data can be read on the LOW-to-HIGH transition of
the read clock RCLKA (RCLKB).
A read and write should not be performed simultaneously
to the offset registers.
Figure 2. Writing to Offset Registers for FIFOs A and B
87
0
Empty Offset (LSB) Reg.
Default Value 007H
80
Full Offset (LSB) Reg.
Default Value 007H
7
80
Empty Offset (LSB)
Default Value 007H
80
Full Offset (LSB)
Default Value 007H
72801 - 256 x 9 x 2
72811 - 512 x 9 x 2
7
7
80
(MSB)
1
00
87
0
Empty Offset (LSB) Reg.
Default Value 007H
80
Full Offset (LSB) Reg.
Default Value 007H
7
80
Empty Offset (LSB)
Default Value 007H
80
Full Offset (LSB)
Default Value 007H
72831 - 2048 x 9 x 2
72841 - 4096 x 9 x 2
7
7
80
80
(MSB)
0000
2
(MSB)
000
3
80
80
(MSB)
0000
2
(MSB)
000
3
80
8
0
80
(MSB)
1
0
87
0
Empty Offset (LSB) Reg.
Default Value 007H
80
Full Offset (LSB) Reg.
Default Value 007H
7
72821 - 1024 x 9 x 2
80
(MSB)
00
1
80
(MSB)
00
1
3034 drw 05


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