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IDT72831L20PF Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT72831L20PF Datasheet(HTML) 8 Page - Integrated Device Technology |
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8 / 21 page  5.15 8 COMMERCIAL TEMPERATURE 72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO ™ 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 OUTPUTS: Full Flag ( FFA FFA, FFB FFB) — FFA (FFB) will go LOW, inhibiting further write operations, when Array A (B) is full. If no reads are performed after reset, FFA (FFB) will go LOW after 256 writes to the 72801's FIFO A (B), 512 writes to the 72811's FIFO A (B), 1024 writes to the 72821's FIFO A (B), 2048 writes to the 72831's FIFO A (B), or 4096 writes to the 72841's FIFO A (B). FFA (FFB) is synchronized with respect to the LOW-to- HIGH transition of the write clock WCLKA (WCLKB). Empty Flag ( EFA EFA, EFB EFB) — EFA (EFB) will go LOW, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that Array A (B) is empty. EFA (EFB) is synchronized with respect to the LOW-to- HIGH transition of the read clock RCLKA (RCLKB). Programmable Almost–Full Flag ( PAFA PAFA, PAFB PAFB) — PAFA ( PAFB) will go LOW when the amount of data in Array A (B) reaches the Almost-Full condition. If no reads are performed after reset, PAFA (PAFB) will go LOW after (256-m) writes to the 72801's FIFO A (B), (512-m) writes to the 72811's FIFO A (B), (1024-m) writes to the 72821's FIFO A (B), (2048-m) TABLE 1: STATUS FLAGS FOR A AND B FIFOS NUMBER OF WORDS IN ARRAY A FFA FFA PAFA PAFA PAEA PAEA EFA EFA NUMBER OF WORDS IN ARRAY B FFB FFB PAFB PAFB PAEB PAEB EFB EFB 72801 72811 72821 00 0 H H L L 1 to n(1) 1 to n(1) 1 to n(1) HH L H (n+1) to (256-(m+1)) (n+1) to (512-(m+1)) (n+1) to (1024-(m+1)) H H H H (256-m)(2) to 255 (512-m)(2) to 511 (1024-m)(2) to 1023 H L H H 256 512 1024 L L H H NUMBER OF WORDS IN ARRAY A FFA FFA PAFA PAFA PAEA PAEA EFA EFA NUMBER OF WORDS IN ARRAY B FFB FFB PAFB PAFB PAEB PAEB EFB EFB 72831 72841 00 H H L L 1 to n(1) 1 to n(1) HH L H (n+1) to (2048-(m+1)) (n+1) to (4096-(m+1)) H H H H (2048-m)(2) to 2047 (4096-m)(2) to 4095 H L H H 2048 4096 L L H H NOTES: 3034 tbl 09 1. n = Empty Offset (n = 7 default value) 2. m = Full Offset (m = 7 default value) writes to the 72831's FIFO A (B), or (4096-m) writes to the 72841's FIFO A (B). FFA (FFB) is synchronized with respect to the LOW-to- HIGH transition of the write clock WCLKA (WCLKB). The offset “m” is defined in the Full Offset Registers. If there is no Full offset specified, PAFA (PAFB) will go LOW at Full-7 words. PAFA (PAFB) is synchronized with respect to the LOW-to- HIGH transition of the write clock WCLKA (WCLKB). Programmable Almost–Empty Flag ( PAEA PAEA, PAEB PAEB) — PAEA (PAEB) will go LOW when the read pointer is "n+1" locations less than the write pointer. The offset "n" is defined in the Empty Offset Registers. If no reads are performed after reset, PAEA (PAEB) will go HIGH after "n+1" writes to FIFO A (B). If there is no Empty offset specified, PAEA (PAEB) will go LOW at Empty+7 words. PAEA (PAEB) is synchronized with respect to the LOW-to- HIGH transition of the read clock RCLKA (RCLKB). Data Outputs (QA0 – QA8, QB0 – QB8 ) — QA0 - QA8 are the nine data outputs for memory array A, QB0 - QB8 are the nine data outputs for memory array B. |
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