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IDT72211L20J Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT72211L20J Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 19 page 5.07 7 IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO ™ 64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES However, writing all offset registers does not have to occur at one time. One or two offset registers can be written and then by bringing the Write Enable 2/Load (WEN2/ LD) pin HIGH, the FIFO is returned to normal read/write operation. When the Write Enable 2/Load (WEN2/ LD) pin is set LOW, and Write Enable 1 ( WEN1) is LOW, the next offset register in sequence is written. The contents of the offset registers can be read on the output lines when the Write Enable 2/Load (WEN2/ LD) pin is set low and both Read Enables ( REN1, REN2) are set LOW. Data can be read on the LOW-to-HIGH transition of the read clock (RCLK). A read and write should not be performed simultaneously to the offset registers. Figure 3. Offset Register Location and Default Values 86 0 Empty Offset (LSB) Reg. Default Value 007H 80 Full Offset (LSB) Reg. Default Value 007H 87 0 Empty Offset (LSB) Reg. Default Value 007H 80 Full Offset (LSB) Reg. Default Value 007H 7 80 Empty Offset (LSB) Default Value 007H 80 Full Offset (LSB) Default Value 007H 72421 - 64 x 9-BIT 72201 - 256 x 9-BIT 72211 - 512 x 9-BIT 7 7 80 (MSB) 1 80 00 80 87 0 Empty Offset (LSB) Reg. Default Value 007H 80 Full Offset (LSB) Reg. Default Value 007H 7 87 0 Empty Offset (LSB) Reg. Default Value 007H 80 Full Offset (LSB) Reg. Default Value 007H 7 80 Empty Offset (LSB) Default Value 007H 80 Full Offset (LSB) Default Value 007H 72221 - 1024 x 9-BIT 72231 - 2048 x 9-BIT 72241 - 4096 x 9-BIT 7 7 80 80 (MSB) 0000 2 (MSB) 000 3 80 (MSB) 00 1 80 80 (MSB) 0000 2 (MSB) 000 3 80 (MSB) 00 1 5 65 80 8 0 80 (MSB) 1 0 2655 drw 05 LD WEN1 WCLK(1) Selection 0 0 Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) 0 1 No Operation 1 0 Write Into FIFO 1 1 No Operation NOTE: 2655 drw 04 1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and read is performed on the LOW-to-HIGH transition of RCLK. Figure 2. Write Offset Register |
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