5.07

9

IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO

™

64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Figure 4. Reset Timing

NOTES:

1. Holding WEN2/

LD HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LD LOW during reset will make the pin act as

a load enable for the programmable flag offset registers.

2. After reset, the outputs will be LOW if

OE = 0 and tri-state if OE = 1.

3. The clocks (RCLK, WCLK) can be free-running during reset.

RS

REN1,

REN2

OE = 1

OE = 0

(2)

EF, PAE

FF, PAF

2655 drw 06

WEN2/

LD

WEN1

(1)