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IDT72821L12PF Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT72821L12PF Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 21 page  5.15 5 COMMERCIAL TEMPERATURE 72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO ™ 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 AC TEST CONDITIONS In Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load See Figure 1 3034 tbl 08 *Includes jig and scope capacitances. Figure 1. Output Load or equivalent circuit AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C) Commercial IDT72801L12 IDT72801L15 IDT72801L20 IDT72801L25 IDT72801L35 IDT72811L12 IDT72811L15 IDT72811L20 IDT72811L25 IDT72811L35 IDT72821L12 IDT72821L15 IDT72821L20 IDT72821L25 IDT72821L35 IDT72831L12 IDT72831L15 IDT72831L20 IDT72831L25 IDT72831L35 IDT72841L12 IDT72841L15 IDT72841L20 IDT72841L25 IDT72841L35 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit fS Clock Cycle Frequency — 83.3 — 66.7 — 50 — 40 — 28.6 MHz tA Data Access Time 2 8 2 10 2 12 3 15 3 20 ns tCLK Clock Cycle Time 12 — 15 — 20 — 25 — 35 — ns tCLKH Clock High Time 5 — 6 — 8 — 10 — 14 — ns tCLKL Clock Low Time 5 — 6 — 8 — 10 — 14 — ns tDS Data Set-up Time 3 — 4 — 5 — 6 — 8 — ns tDH Data Hold Time 0 — 1 — 1 — 1 — 2 — ns tENS Enable Set-up Time 3 — 4 — 5 — 6 — 8 — ns tENH Enable Hold Time 0 — 1 — 1 — 1 — 2 — ns tRS Reset Pulse Width(1) 12 — 15 — 20 — 25 — 35 — ns tRSS Reset Set-up Time 12 — 15 — 20 — 25 — 35 — ns tRSR Reset Recovery Time 12 — 15 — 20 — 25 — 35 — ns tRSF Reset to Flag Time and Output Time — 12 — 15 — 20 — 25 — 35 ns tOLZ Output Enable to Output in Low-Z(2) 0— 0— 0— 0— 0— ns tOE Output Enable to Output Valid 3 7 3 8 3 10 3 13 3 15 ns tOHZ Output Enable to Output in High-Z(2) 3 7 3 8 310 3 13 315 ns tWFF Write Clock to Full Flag — 8 — 10 — 12 — 15 — 20 ns tREF Read Clock to Empty Flag — 8 — 10 — 12 — 15 — 20 ns tPAF Write Clock to Programmable Almost-Full Flag — 8 — 10 — 12 — 15 — 20 ns tPAE Read Clock to Programmable Almost-Empty Flag — 8 — 10 — 12 — 15 — 20 ns tSKEW1 Skew Time Between Read 5 — 6 — 8 — 10 — 12 — ns Clock and Write Clock for Empty Flag and Full Flag tSKEW2 Skew Time Between Read Clock 22 — 28 — 35 — 40 — 42 — ns and Write Clock for Programmable Almost-Empty Flag and Programmable Almost-Full Flag NOTES: 3034 tbl 07 1. Pulse widths less than minimum values are not allowed. 2. Values guaranteed by design, not currently tested. 30pF* 1.1K 5V 680 Ω D.U.T. 3034 drw 03 |
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