5.15

9

COMMERCIAL TEMPERATURE

72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO

™

256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9

RSA (RSB)

RENA1, RENA2

(

RENB1, RENB2)

OEA (OEB) = 1

OEA (OEB) = 0

(2)

EFA, PAEA

(

EFB, PAEB)

FFA, PAFA

(

FFA, PAFA)

3034 drw 06

WENA1

(

WENB1)

WENA2/

LDA

(WENB2/

LDB)

(1)

NOTES:

1. Holding WENA2/

LDA (WENB2/LDB) HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LDA (WENB2/LDB) LOW during

reset will make the pin act as a load enable for the programmable flag offset registers.

OEA (OEB) = 0 and tri-state if OEA (OEB) = 1.

3. The clocks RCLKA, WCLKA (RCLKB, WCLKB) can be free-running during reset.

Figure 4. Reset Timing