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ADSP-21366KBC-1AA Datasheet(PDF) 5 Page - Analog Devices |
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ADSP-21366KBC-1AA Datasheet(HTML) 5 Page - Analog Devices |
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5 / 52 page  ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. A | Page 5 of 52 | December 2006 SHARC FAMILY CORE ARCHITECTURE The ADSP-2136x is code-compatible at the assembly level with the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-2136x shares architectural features with the ADSP-2126x and ADSP-2116x SIMD SHARC processors, as detailed in the following sections. SIMD Computational Engine The ADSP-2136x contains two computational processing ele- ments that operate as a single-instruction multiple-data (SIMD) engine. The processing elements are referred to as PEX and PEY and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY may be enabled by setting the PEYEN mode bit in the MODE1 register. When this mode is enabled, the same instruction is executed in both processing ele- ments, but each processing element operates on different data. This architecture is efficient at executing math intensive signal processing algorithms. Entering SIMD mode also has an effect on the way data is trans- ferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the regis- ter file. Independent, Parallel Computation Units Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all opera- tions in a single cycle. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit single-precision floating-point, 40-bit extended-precision floating-point, and 32-bit fixed-point data formats. Data Register File A general-purpose data register file is contained in each pro- cessing element. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the ADSP-2136x enhanced Figure 2. ADSP-2136x System Sample Configuration DAI SPI ID P SR C SPD IF SP OR T0-5 SC LK 0 SD 0A SFS0 SD 0B SR U DAI_P1 DA I_ P2 DA I_ P3 DAI_P 18 DAI _P 19 DA I_ P2 0 DAC (OPTI ONA L) ADC (OPTI ONA L) FS CLK SD AT FS CLK SD AT 3 CLOC K FLA G3-1 2 2 CLK IN XTA L CLK _CFG1-0 B OOTC FG1 -0 ADDR PARALLEL POR T RAM I/O D EVI CE OE DATA WE RD WR CLKOUT ALE AD 1 5-0 LA TCH RES ET JTA G 6 ADSP-2136x CS FLA G0 PCG B PC GA CLK FS TIME R S |
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