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NCV7708DWG Datasheet(PDF) 10 Page - ON Semiconductor

Part # NCV7708DWG
Description  Double Hex Driver
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NCV7708DWG Datasheet(HTML) 10 Page - ON Semiconductor

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NCV7708
http://onsemi.com
10
DETAILED OPERATING DESCRIPTION
General
The NCV7708 Double Hex Driver provides drive
capability for 3 independent H−Bridge configurations, or 6
High Side configurations with 6 Low Side configurations, or
any combination of arrangements. Each output drive is
characterized for a 500 mA load and has a typical 1.0 A surge
capability (at 12 V). Strict adherence to integrated circuit die
temperature is necessary. Maximum die temperature is
150
°C. This may limit the number of drivers enabled at one
time. Output drive control and fault reporting is handled via
the SPI (Serial Peripheral Interface) port.
An Enable function (EN) provides a low quiescent sleep
current mode when the device is not being utilized. No data
is stored when the device is in sleep mode. A pull down
current source is provided on the EN input to ensure the
device is off if the input signal is lost. Pull down current
sources are also provided on the SI and SCLK inputs. A pull
up current source is provided for the CSB input for the same
reason. A loss of signal pulls the CSB input high to stop any
spurious signals into the SPI port.
Power Up/Down Control
An under voltage lockout circuit prevents the output
drivers from turning on unintentionally. This control is
provided by monitoring the voltages on the VS1, VS2, and
VCC pins. Each analog power pin (VS1 or VS2) powers their
respective output drivers (VS1 powers OUTH1, OUTH2,
OUTH3, all 6 charge pumps and all 6 low side pre−drivers.
VS2 powers OUTH4, OUTH5, and OUTH6). All drivers are
initialized in the off (high impedance) condition, and will
remain off regardless of the status of VCC. This allows
power up sequencing of VCC, VS1, and VS2 up to the user.
The voltage on VS1 and VS2 should be operated at the same
potential.
A built−in hysteresis on the under voltage threshold is
included to prevent an unknown region on the power pins.
After a device has powered up and the output drivers are
allowed to turn on, the output drivers will not turn off until
the voltage on the supply pins is reduced from the initial
under voltage threshold, or if shut down by either a SPI
command or a fault condition.
Internal power−up circuitry on the logic supply pin
supports a smooth turn on transition. VCC power up resets
the internal logic such that all output drivers will be off as
power is applied. Exceeding the under voltage lockout
threshold on VCC allows information to be input through the
SPI port for turn on control. Logic information remains
intact over the entire VS1 and VS2 voltage range.
Current Limitation
Input bit 13 (OCD) controls the action of driver shutoff
during current limit. With a 0 for bit 13, there is no driver
shutoff, and the drivers current limit at 3 A. With a 1 for input
bit 13, the output drivers shut off when the shutdown
threshold current is passed. Devices can be turned back on
via the SPI port. Note: high currents could cause a high rise
in die temperature. Devices will not turn on if the die
temperature exceeds the thermal shutdown temperature.
Over Current Detection Shut Down
OCD Input
Bit 13
OUTx OCD
Condition
Output Data Bit 13 Over
Load Detect (OLD) Status
OUTx Status
Current Limit
of all Drivers
0
0
0
Unchanged
3 A
0
1
1 (Need SRR to reset)
Unchanged
3 A
1
0
0
Unchanged
3 A
1
1
1 (Need SRR to reset)
OUTx Latches Off (Need SRR to reset)
3 A
Under load Detection
The under−load detection is accomplished by monitoring
the current from each output driver. A minimum load current
(this is the maximum open circuit detection threshold) is
required when the drivers are turned on. If the under−load
circuit detection threshold has been crossed for more than
the under−load delay time, the bit indicator (output bit #14)
for open circuit will be set to a 1. In addition, the offending
driver will be turned off only if input bit 14 (ULD) is set to
1 (true).
Under Load Detection Shut Down
ULD Input
Bit 14
OUTx ULD
Condition
Output Data Bit 14 Under
Load Detect (ULD) Status
OUTx Status
0
0
0
Unchanged
0
1
1 (Need SRR to reset)
Unchanged
1
0
0
Unchanged
1
1
1 (Need SRR to reset)
OUTx Latches Off (Need SRR to reset)


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