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NCP5220 Datasheet(PDF) 1 Page - ON Semiconductor

Part # NCP5220
Description  3?뭝n?? PWM Dual Buck and Linear Power Controller
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NCP5220 Datasheet(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2004
November, 2004 − Rev. 4
1
Publication Order Number:
NCP5220/D
NCP5220
3−in−1 PWM Dual Buck and
Linear Power Controller
The NCP5220 3−in−1 PWM a Dual Buck and Linear Power
Controller, is a complete power solution for MCH and DDR memory.
This IC combines the efficiency of PWM controllers for the VDDQ
supply and the MCH core supply voltage with the simplicity of linear
regulator for the VTT termination voltage.
This IC contains two synchronous PWM buck controller for driving
four external N−Ch FETs to form the DDR memory supply voltage
(VDDQ) and the MCH regulator. The DDR memory termination
regulator (VTT) is designed to track at the half of reference voltage
with sourcing and sinking current.
Protective features include, soft−start circuitry, undervoltage
monitoring of 5VDUAL, BOOT voltage and thermal shutdown. The
device is housed in a thermal enhanced space−saving DFN−20
package.
Features
Pb−Free Package is Available*
Incorporates Synchronous PWM Buck Controllers for VDDQ and
VMCH
Integrated Power FETs with VTT Regulator Source/Sink up to 2.0 A
All External Power MOSFETs are N−Channel
Adjustable VDDQ and VMCH by External Dividers
VTT Tracks at Half the Reference Voltage
Fixed Switching Frequency of 250 kHz for VDDQ and VMCH
Doubled Switching Frequency of 500 kHz for VDDQ Controller in
Standby Mode to Optimize Inductor Current Ripple and Efficiency
Soft−Start Protection for All Controllers
Undervoltage Monitor of Supply Voltages
Overcurrent Protections for DDQ and VTT Regulators
Fully Complies with ACPI Power Sequencing Specifications
Short Circuit Protection Prevents Damage to Power Supply Due to
Reverse DIMM Insertion
Thermal Shutdown
5x6 DFN−20 Package
Typical Applications
DDR I and DDR II Memory and MCH Power Supply
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
PIN CONNECTIONS
Device
Package
Shipping†
ORDERING INFORMATION
NCP5220MNR2
DFN−20
2500 Tape & Reel
NCP5220 = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
MARKING
DIAGRAM
COMP
SS
SW_DDQ
FBDDQ
PGND
BOOT
VTT
5VDUAL
VDDQ
AGND
FBVTT
SLP_S5
FB1P5
BG_DDQ
TG_DDQ
COMP_1P5
SLP_S3
TG_1P5
BG_1P5
GND_1P5
DFN−20
MN SUFFIX
CASE 505AB
1
20
NCP5220
AWLYYWW
1
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
NOTE: Pin 21 is the thermal pad
on the bottom of the device.
NCP5220MNR2G
DFN−20
(Pb−Free)
2500 Tape & Reel
http://onsemi.com


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