© Semiconductor Components Industries, LLC, 2005

January, 2005 − Rev. 4

1

Publication Order Number:

NCP5210/D

NCP5210

3−in−1 PWM Dual Buck

and Linear DDR Power

Controller

The NCP5210, 3−in−1 PWM Dual Buck and Linear DDR Power

Controller, is a complete power solution for MCH and DDR memory.

This IC combines the efficiency of PWM controllers for the VDDQ

supply and the MCH core supply voltage with the simplicity of linear

regulator for the VTT termination voltage.

This IC contains two synchronous PWM buck controller for driving

four external N−Ch FETs to form the DDR memory supply voltage

(VDDQ) and the MCH regulator. The DDR memory termination

regulator (VTT) is designed to track at the half of the reference voltage

with sourcing and sinking current.

Protective features include, soft−start circuitry, undervoltage

monitoring of 5VDUAL and BOOT voltage, and thermal shutdown.

The device is housed in a thermal enhanced space−saving

QFN−20 package.

Features

VMCH

Standby Mode to Optimize Inductor Current Ripple and Efficiency

to Reverse DIMM Insertion

Applications

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

PIN CONNECTIONS

ORDERING INFORMATION

NCP5210 = Specific Device Code

A

= Assembly Location

WL

= Wafer Lot

YY

= Year

WW

= Work Week

MARKING

DIAGRAM

COMP

SS

SW_DDQ

FBDDQ

PGND

BOOT

VTT

5VDUAL

VDDQ

AGND

FBVTT

DDQ_REF

FB1P5

BG_DDQ

TG_DDQ

COMP_1P5

BUF_Cut

TG_1P5

BG_1P5

GND_1P5

QFN−20

MN SUFFIX

CASE 505AB

1

20

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

NOTE: Pin 21 is the thermal pad

on the bottom of the device.

Device

Package

NCP5210MNR2

QFN−20

2500 Tape & Reel

NCP5210MNR2G

QFN−20

(Pb−Free)

2500 Tape & Reel

1

NCP5210

AWLYYWW

http://onsemi.com