NCP1595, NCP1595A

http://onsemi.com

10

DETAILED OPERATING DESCRIPTION

Introduction

NCP1595 operates as a current mode buck converter with

switching frequency at 1.0 MHz. The P−Channel main

switch is set by the positive edge of the clock cycle going

into the PWM latch. The main switch is reset by the

PWM latch in the following three cases:

1. PWM comparator output trips as the peak inductor

current signal reaches a threshold level established

by the error amplifier.

2. The inductor current has reached the current limit.

3. Overvoltage at output occurs.

After a minimum dead time, the N−Channel synchronized

switch will turn on and the inductor current will ramp down.

If the inductor current ramps down to zero before the

initiation of next clock cycle, the regulator runs at

discontinuous conduction mode (DCM). Otherwise the

regulator is at continuous conduction mode (CCM). The

N−Channel switch will turn off when the clock cycle starts.

The duty cycle is given by the ratio of output voltage to input

voltage. The duty cycle is allowed to go to 100% to increase

transient load response when going from light load to heavy

load.

Error Amplifier and Slope Compensation

A fully internal compensated error amplifier is provided

inside NCP1595. No external circuitry is needed to stabilize

the device. The error amplifier provides an error signal to the

PWM comparator by comparing the feedback voltage

(800 mV) with internal voltage reference of 1.2 V.

Current mode converter can exhibit instability at duty

cycles over 50%. A slope compensation circuit is provided

inside NCP1595 to overcome the potential instability. Slope

compensation consists of a ramp signal generated by the

synchronization block and adding this to the inductor

current signal. The summed signal is then applied to the

PWM comparator.

Soft−Start and Current Limit

A soft start circuit is internally implemented to reduce the

in−rush current during startup. This helps to reduce the

output voltage overshoot.

The current limit is set to allow peak switch current in

excess of 2 A. The intended output current of the system is

1.5 A. The ripple current is calculated to be approximately

350 mA with a 3.3

mH inductor. Therefore, the peak current

at 1.5 A output will be approximately 1.7 A. A 2 A set point

will allow for transient currents during load step. The current

limit circuit is implemented as a cycle−by−cycle current

limit. Each on−cycle is treated as a separate situation.

Current limiting is implemented by monitoring the

P−Channel switch current buildup during conduction with a

current limit comparator. The output of the current limit

comparator resets the PWM latch, immediately terminating

the current cycle.

Over−Voltage Protection

Overvoltage occurs when the feedback voltage exceeds

5% of its regulated voltage. In this case, the P−Channel main

switch will be reset and the N−Channel synchronized switch

is turn on to sink current from the output voltage which helps

to drop its feedback voltage back to the regulated voltage.

Thermal Shutdown

Internal Thermal Shutdown circuitry is provided to

protect the integrated circuit in the event when maximum

junction temperature is exceeded. When activated, typically

at 160

°C, the shutdown signal will disable the P−Channel

and N−Channel switch. The thermal shutdown circuit is

designed with 30

°C of hysteresis. This means that the

switching will not start until the die temperature drops by

this amount. This feature is provided to prevent catastrophic

failures from accidental device overheating. It is not

intended as a substitute for proper heat sinking.

NCP1595 is contained in the thermally enhanced

DFN package.