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ADC08B3000 Datasheet(PDF) 30 Page - National Semiconductor (TI) |
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ADC08B3000 Datasheet(HTML) 30 Page - National Semiconductor (TI) |
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30 / 32 page  2.0 Applications Information (Continued) To maximize the removal of heat from the package, a ther- mal land pattern must be incorporated on the PC board within the footprint of the package. The exposed pad of the device must be soldered down to ensure adequate heat conduction out of the package. The land pattern for this exposed pad should be at least as large as the5x5mmof the exposed pad of the package and be located such that the exposed pad of the device is entirely over that thermal land pattern. This thermal land pattern should be electrically con- nected to ground. A clearance of at least 0.5 mm should separate this land pattern from the mounting pads for the package pins. Since a large aperture opening may result in poor release, the aperture opening should be subdivided into an array of smaller openings, similar to the land pattern of Figure 13. To minimize junction temperature, it is recommended that a simple heat sink be built into the PCB. This is done by including a copper area of about 2 square inches (6.5 square cm) on the opposite side of the PCB. This copper area may be plated or solder coated to prevent corrosion, but should not have a conformal coating, which could provide some thermal insulation. Thermal vias should be used to connect these top and bottom copper areas. These thermal vias act as "heat pipes" to carry the thermal energy from the device side of the board to the opposite side of the board where it can be more effectively dissipated. The use of 9 to 16 thermal vias is recommended. The thermal vias should be placed on a 1.2 mm grid spacing and have a diameter of 0.30 to 0.33 mm. These vias should be barrel plated to avoid solder wicking into the vias during the soldering process as this wicking could cause voids in the solder between the package exposed pad and the ther- mal land on the PCB. Such voids could increase the thermal resistance between the device and the thermal land on the board, which would cause the device to run hotter. If it is desired to monitor die temperature, a temperature sensor may be mounted on the heat sink area of the board near the thermal vias. .Allow for a thermal gradient between the temperature sensor and the ADC08B3000 die of θ J-PAD times typical power consumption = 2.8 x 1.9 = 5.3˚C. Allow- ing for 6.3˚C, including some margin for temperature drop from the pad to the temperature sensor, then, would mean that maintaining a maximum pad temperature reading of 123.7˚C will ensure that the die temperature does not ex- ceed 130˚C, assuming that the exposed pad of the ADC08B3000 is properly soldered down and the thermal vias are adequate. (The inaccuracy of the temperature sen- sor is addtional to the above calculation). 2.7 LAYOUT AND GROUNDING Proper grounding and proper routing of all signals are es- sential to ensure accurate conversion. A single ground plane should be used, instead of splitting the ground plane into analog and digital areas. Since digital switching transients are composed largely of high frequency components, the skin effect tells us that total ground plane copper weight will have little effect upon the logic-generated noise. Total surface area is more important than is total ground plane volume. Coupling between the typically noisy digital circuitry and the sensitive analog cir- cuitry can lead to poor performance that may seem impos- sible to isolate and remedy. The solution is to keep the analog circuitry well separated from the digital circuitry. High power digital components should not be located on or near any linear component or power supply trace or plane that services analog or mixed signal components as the resulting common return current path could cause fluctuation in the analog input “ground” return of the ADC, causing excessive noise in the conversion result. Generally, we assume that analog and digital lines should cross each other at 90˚ to avoid getting digital noise into the analog path. In high frequency systems, however, avoid crossing analog and digital lines altogether. The input clock lines should be isolated from ALL other lines, analog AND digital. The generally accepted 90˚ crossing should be avoided as even a little coupling can cause problems at high frequencies. Best performance at high frequencies is ob- tained with a straight signal path. The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. This is especially important with the low level drive required of the ADC08B3000. Any external component (e.g., a filter capaci- tor) connected between the converter’s input and ground should be connected to a very clean point in the analog ground plane. All analog circuitry (input amplifiers, filters, etc.) should be separated from any digital components. 2.8 DYNAMIC PERFORMANCE The ADC08B3000 is a.c. tested and its dynamic perfor- mance is guaranteed. To meet the published specifications and avoid jitter-induced noise, the clock source driving the CLK input must exhibit low rms jitter. The allowable jitter is a function of the input frequency and the input signal level, as described in Section 2.3. It is good practice to keep the ADC input clock line as short as possible, to keep it well away from any other signals and to treat it as a transmission line. Other signals can introduce jitter into the input clock signal. The clock signal can also introduce noise into the analog path if not isolated from that path. Best dynamic performance is obtained when the exposed pad at the back of the package has a good connection to ground. This is because this path from the die to ground is a lower impedance than offered by the package pins. 20160121 FIGURE 13. Recommended Package Land Pattern www.national.com 30 |
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